Hot Carrier Injection Reliability Research Articles

A novel MOSFET with lateral–vertical charge coupling for extremely low C gd

A novel MOSFET with lateral–vertical charge coupling (LVCC-MOSFET) is proposed in this paper. Lateral charge coupling is enabled by a metal field plate, lightly doped drain and P-Epi layer to reduce the C gd. Vertical charge coupling is enabled by a shield gate, sinker and P-Epi layer to support a high breakdown voltage (BV) and further reduce the C gd. By combining both lateral charge coupling and vertical charge coupling, which is first proposed in low-voltage power MOSFETs, the trade-off relationship between BV, R on and C gd can be significantly improved. It is verified by both small-signal analysis and transient capacitance simulation that the gate-to-drain capacitance of the proposed LVCC-MOSFET can be reduced by more than 99% without deterioration of BV and R on. The LVCC-MOSFET achieves 93.7% reduction in Q gd, and R on × Q gd is only 0.81 mΩ·nC, which is reduced by 93.9%. Furthermore, E on and E off can be reduced by 73.6% and 53.8%, respectively. The hot carrier injection reliability can be enhanced by reducing the electric field and the impact ionization generation rate near the drain-side gate oxide. Moreover, the LVCC-MOSFET can be feasibly manufactured with compatible fabrication process flow, and only three extra steps are needed.

Hot Carrier Injection (HCI) Reliability of Fabricated Y-gate HEMT with Various Top Length

Device degradation due to hot carrier injection (HCI) in different Y-gate HEMT devices is thoroughly analyzed. To further understand the HCI reliability of the Y-gate HEMT devices, the device is fabricated with AlGaN/GaN structure with different top lengths (Ltop). An HCI stress time of 6000 s was conducted on these devices, while V t stability in other stress time domains, leakage current, and transconductance degradation are also discussed. In this work, we have demonstrated that increasing the LTop length could avoid the virtual gate effect and disperse the influence of the electric field under HCI stress. Furthermore, the effects of trapping in various locations, such as in the bulk SiN or AlGaN/GaN interface has been discussed. These trapping effects caused by the HCI stress might be the source of the Vth shift. Overall, The large Y-gate HEMT showed the lowest degradation of DC characteristics after the long HCI stress test.

Hot Carrier Injection Reliability of Fabricated N- and P-Type Multi FinFETs with Different TiN Stacks

Device degradation due to hot carrier injection (HCI) in multi-fin 20 nm and 10 nm N- and P-type FinFET devices are thoroughly analyzed. To further understand the HCI reliability of the four FinFET devices, the device is fabricated with a standard Vt base and low Vt base gate stacks with different work functions. It is evident that: (i) The standard Vt device sustains lower effective stress bias due to the difference in threshold voltage, resulting in a more stable threshold voltage than the low Vt base device, and (ii) the transconductance of the single N- and P-type FinFET is more severely degraded than the multi-fin N- and P-type FinFET, mainly because multi N- and P-type Finfet has coupe effect, which effectively reduces the impact of HCI.

Hot Carrier Injection Reliability in Nanoscale Field Effect Transistors: Modeling and Simulation Methods

Hot carrier injection (HCI) can generate interface traps or oxide traps mainly by dissociating the Si-H or Si-O bond, thus affecting device performances such as threshold voltage and saturation current. It is one of the most significant reliability issues for devices and circuits. Particularly, the increase in heat generation per unit volume due to high integration density of advanced integrated circuits leads to a severe self-heating effect (SHE) of nanoscale field effect transistors (FETs), and low thermal conductivity of materials in nanoscale FETs further aggravates the SHE. High temperature improves the HCI reliability in the conventional MOSFET with long channels in which the energy of carriers can be relaxed. However, high temperature due to severe SHE deteriorates HCI reliability in nanoscale FETs, which is a big concern in device and circuit design. In this paper, the modeling and simulation methods of HCI in FETs are reviewed. Particularly, some recently proposed HCI models with consideration of the SHE are reviewed and discussed in detail.

NBTI and HCI Aging Prediction and Reliability Screening During Production Test

With the semiconductor manufacturing technology approaching to 14 nm and below, the reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging mechanisms, including negative bias temperature instability (NBTI) and hot carrier injection (HCI). Furthermore, significant process variations differ the aging degradation rate of each individual IC, which causes significant failure time differences even for the ICs belonging to the same lot. Therefore, to select devices for the applications with various reliability requirements, it is necessary to conduct efficient predictive reliability screening during production test at time-zero. In this article, a fast time-zero aging prediction and predictive screening methodology based on a novel on-chip architecture named ZeroScreen is proposed. The pattern-based aging screening time is limited to 8.14 ms per device considering 50-MHz test clock frequency and 6.6- $\mu \text{s}$ automatic test equipment (ATE) voltage settling time. In the experiment, fresh 45-nm FPGA devices and 130-nm ASIC chips are projected into four reliability bins with ZeroScreen-based aging prediction at time-zero. According to the silicon data, the reliability screening errors of ZeroScreen for the 45-nm FPGA chips are less than 6.5% and 4.3% for static and dynamic stress cases, respectively. And the screening errors for the 130 nm ASIC chips are close to 0, for both static and dynamic stress cases.

Study of HCI Reliability for PLDMOS

In this paper, we demonstrate electrical degradation due to hot carrier injection (HCI) stress for PLDMOS device. The lower gate current and the IDsat degradation at low gate voltage (VGS) and high drain voltage (VDS) is investigated. Hot Electrons, generated by impact ionization during stress, are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel. Increase of the drain-source current is induced by the negative fixed oxide charges. The physical model of the degradation has been proven combining experimental data and TCAD simulations.

Study of impact of LATID on HCI reliability for LDMOS devices

This paper demonstrates electrical degradation due to Hot Carrier Injection (HCI) stress for nLDMOS devices with different Large Angle Tilted Implantation Doping (LATID) techniques for p-body. It seems that optimization of the device with LATID angle for p-body in nLDMOS is important to achieve improved HCI performance and observed that HCI degradation is minimum for 300 LATID for p-body. We observed Si/SiO2 interface trap under various stress conditions, were evaluation based on our Sentaurus simulation, and we compare trapped charge density and distribution for various LATID angles and it was less for 300 tilt. Trap-related models were employed to perform Ron and Id,sat degradations during the HCI stress test. So nLDMOS device with 300 tilt angle for p-body shows better HCI performance compared to other LATID. Also our new proposed device structure shows less HCI degradations when compared with silicon data of HCI degradations for other nLDMOS structure.

Effects of Deuterium Incorporation on Performance and Reliability of Gate-Last High-k/Metal Gate CMOS Devices

Deuterium annealing has been widely used to help improve hot carrier injection (HCI) reliability of CMOS devices[1]. With introduction of high-k, and especially the gate-last metal gate processes, which decouples the high temperature annealing process, the effectiveness of D2 anneal is further investigated in this report. Especially, 20nm gate-last high-k/metal gate planar transistor was characterized in terms of threshold, gate leakage, charge pumping current, and reliability with and without D2 anneal and show that D2 anneal is very effective in suppressing HCI by up to ~3x. We also show that D2 anneal continues to be effective in 14nm 3-D FinFET transistors. The gate length used in this experiment is 20nm and the width is 1um for the 20nm node gate-last planar transistors. For annealing, pure deuterium gas (D2) is applied to all samples at <300C with various pressures, and no deuterium annealing samples were used as reference control sample. The passivation rate k2 for between Si and D2 reaction and Vth can be expressed by eq. (1) and (2). As the deuterium pressure goes up, the passivation rate also increases and as a result, the interface trap density (Dit) reduces. Interface trap generation induced substrate current (ICP) was measured by the charge pumping technique in Fig. 1. Process applying the highest annealing pressure results in the lowest ICP. In other words, it explicitly explains that higher D2 pressure had higher D2 absorption rate at the Si/SiO2 interfaces as expressed in eq. (1). Specially in eq. (2), Qit is dependent on the surface potential, which is dependent on the gate voltage. As a result, the decrease in Qit causes successive threshold voltage increase as shown in Fig. 2. PMOS had higher sensitivity to Qit as its performance and reliability characteristics heavily rely on the IL-interface, whereas, NMOS depends more on the high-k region[3]. In addition, Qot, which is a cause for gate leakage current in off-state, can be suppressed through the diffusion of deuterium after annealing. Off-leakage current at subthreshold region decreases by more than 30% both in annealed P/NMOS devices in our experiment. Deuterium annealing process can improves not only device performance but also reliability. Fig. 3 shows HCI and BTI reliability versus stress time respectively. Fig. 3 represents that D2 annealing process improves hot carrier reliability by up to ~3x at 5000sec stress time for PMOS and ~2x for NMOS. Comparing with conventional hydrogen annealing process, deuterium has bigger mass and approximately 100 times slower desorption rate than hydrogen from the silicon[4], so D2 annealing process had less Vth change was anticipated. But, un-optimized additional annealing could also detach the deuterium from the silicon interface, that can cause increase in the number of dangling bonds in silicon interface. As shown in Fig. 3, there is a big improvement in HCI reliability, whereas, there are no significant differences in BTI reliability. These phenomenon is expected by deuterium desorption mainly due to the channel hot carriers. The channel hot carriers results in the reappearance of the interface defects, and degradation during HCI. Threshold voltage shift as a function of various BTI stress temperature with high pressure annealed wafer was extracted, and thermal activation energy of ~0.2eV was found from the temperature dependence in 20nm gate-last high-k/metal gate CMOS device. Fig. 4 shows the charge pumping result in 14nm FinFET devices. Comparison of ICP between 1x anneal (after M1 process) and 2x anneals (M1, and Final Metal) is shown. There is very small incremental change with 1x D2 anneals at the final metal layer. It means that D2 diffusion process is not the rate-limiting step, and the number of D2 annealing time is negligible in 3-D FinFET devices. We also verify hot carrier impact on the devices with different oxide thickness. More degradation is found in EG than SG as shown in Table 1. It is expected that higher voltage stress during HCI can easily detach the deuterium near Si interfaces in EG than SG, it causes more Vth shift degradation in EG. In conclusion, deuterium incorporation has improved HCI by 2x while achieving higher performance in 20nm gate-last high-k/metal gate technology. The effect of D2 anneal is highly expected to be continued in 14nm 3-D FinFET device. In the near future, D2 impacts using various split conditions on 14nm 3-D devices will be more deeply studied. References Kangguo Cheng, et al., Microelectronic engineering 56, pp353-358, 2001 Ki-Dan Bae, et al., ECS transaction 58 (70), pp3-7, 2013 Sangwoo Pae et al., IRPS, pp352-357, 2008 Jae-Sung Lee, Transactions on electrical and electronic materials, vol. 13, No. 4, pp188-191, August 25, 2012 Figure 1

Gate length dependence of hot carrier injection degradation in short channel silicon on insulator planar MOSFET

With the continued device scaling and the introduction of new device structures, MOSFET reliability phenomena arising from the hot carrier injection (HCI) stress have received extensive attention from both the academia and the industry community. In this work, the degradations of ultra-scaled silicon on insulator (SOI) MOSFETs under the HCI stress are investigated on devices of different gate lengths (L=30-150 nm). Our experimental data demonstrate that the time evolutions of the threshold voltage change (Vth) under the HCI stress for different gate length devices are the same, and the magnitude of Vth reduces for the shorter devices. The degradation of the device under the HCI stress should be due to both the channel hot carrier (CHC) effect and the bias temperature instability (BTI) effect. The distribution and magnitude of the electric field along the MOSFET's channel are analyzed. It is confirmed that besides the well-known CHC effect in the depletion region close to the drain side, a strong BTI effect co-exists in the channel close to the source side. This degradation mechanism is different from the conventional HCI stress. With the gate length decreasing, the contribution of the aforementioned BTI effect becomes larger, and it dominates in the degradation. One feature of the BTI effects is that the corresponding degradation is small when the gate length is short. This is consistent with our experimental result that the change of Vth is small for the device of short gate length under the accelerated HCI stress. The time evolution of Vth can be described by the equation Vth=A•tn, where A is a constant, t is the stress time, and n is the power law exponent obtained by the curve fitting. In this study, the power law exponent n of pMOSFET is larger than that of nMOSFET. This experimental fact can lead to the point that the BTI effect exists during the HCI stress because the BTI effect in ultra-scaled pMOSFETs is more significant than that in nMOSFETs. The stress-recover experiments of the HCI stress on MOSFTTs show larger recovery in device of shorter gate length. It is found that the ratio of the recovery to the total degradation in the 30 nm gate-length device is almost twice as large as that in the 150 nm device. The degradation from the CHC effect has no recovery, and the larger recovery in the shorter-channel device implies the larger component of the BTI degradation. Another intriguing fact is that our experimental result on SOI MOSFET is inconsistent with the recently reported result on FinFET. We argue that the reported stronger HCI degradation in FinFET may not be ascribed only to the stronger electric field in the shorter channel, but also to the fact that the FinFET' channel is three-dimensionally surrounded by the gate dielectric. This kind of three-dimensional structure significantly increases the chance for electrons or holes to be injected into the dielectric layer. Therefore the HCI reliability of planar SOI MOSFETs may be better than that of FinFETs at the same level of gate length. In conclusion, the BTI effect is an important source of the degradation during the HCI stress in ultra-short-channel device, and it is no more negligible in analyzing the underlying physical mechanism.

Effect of Oxidation Enhanced Diffusion on Hot Carrier Injection Induced Degradation in N-Type High-Voltage DDDMOSFET

This paper investigates how the oxidation enhanced diffusion effect influences the reliability of hot carrier injection (HCI) in N-type high-voltage double-diffused drain MOSFET (DDDMOSFET). The oxidation enhanced diffusion influences impurity diffusion in silicon evidently, thus changes the device characteristic and reliability. By NDD drive-in at high temperature with N2 + O2 mixed atmosphere, we make use of the oxidation enhanced diffusion effect in NDD region of N-type HV DDDMOSFET to improve the HCI reliability. And the results are accordant with reliability simulation of TCAD softwar.

Impact of Gate-Induced Strain on MuGFET Reliability

Hot carrier injection (HCI) reliability and negative bias temperature instability (NBTI) of multiple-gate field-effect transistors (MuGFETs) with highly tensile metal gate electrodes were investigated. The results were compared with those from control devices with poly-Si gate electrodes. It was found that gate strain boosts performance without any detrimental effect on HCI or NBTI reliability, indicating MuGFET compatibility with strained silicon technology. The impact of fin width (W fin) scaling was also investigated. HCI reliability improves with W fin scaling, whereas NBTI reliability degrades with W fin scaling. The same W fin scaling trends were observed in both strained and unstrained devices.