Hold Circuit Research Articles

Very Low-Voltage Analog Signal Processing Based on Quasi-Floating Gate Transistors

A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.

Capacitor matching insensitive algorithmic ADC requiring no calibrations

A novel implementation of the algorithmic ADC is proposed in this paper. The ADC is based on an algorithmic 1.5-bit stage in which voltage multiplication is replaced by voltage addition. A floating voltage hold circuit is proposed which enables the accurate addition of signal voltages without requiring precision components. An experimental 12 bit 3.3 MS/s algorithmic ADC in 0.25 μm standard CMOS is described. It occupies 0.15 mm 2 of die area and dissipates 5.5 mW. The power and area FOMs are well below those previously reported for 1.5-bit stage algorithmic ADCs.

On the sufficiently small sampling period for the convenient tuning of fractional-order hold circuits

Remarkable improvement in the performance of digitally handled systems may be achieved by using properly adjusted fractional-order hold circuits. Nevertheless, the tuning methods formerly proposed in the bibliography are exclusively applicable for a certain range of sufficiently small sampling periods. Such a range is analytically obtained and its significance for the applicability of such methods is discussed.

A Position-Sensorless IPM Motor Drive System Using a Detection Circuit of Current Variations

This paper proposes a new circuit configuration for a position-sensorless drive system using an interior permanent magnet synchronous motor (IPM motor) rated at 3.7kW. The configuration can decrease the number of the sample and hold circuits to four, though fourteen sample and hold circuits are required for the conventional system. In addition, the configuration makes it efficient to detect current variations. It is shown experimentally that the drive system has good position estimation characteristics with absolute and relative errors within ±2 deg and ±0.5 deg in electrical angle, respectively. Moreover, the position control response is improved by adding current control loops to the position-sensorless drive system.

A Fast Macro-Model for Substrate Coupling and Ground Bounce Induced Substrate Noise Simulation in Mixed Signal VLSI

This paper discusses a novel substrate modeling technique for the simulation of substrate noise in mixed signal VLSI systems. This model yields to easy merger with the SPICE simulation netlist for the complete pre and post layout estimation of substrate noise effects in large mixed signal VLSI chips. Compared to previous numerous efforts in substrate noise modeling ranging from finite element methods (FEM) to boundary elements methods (BEM), this model, based on a finite sheet resistor slicing scheme also incorporates the effect of supply rail bounce due to bonding wire inductances, and, provides realistic estimates of substrate noise effects with a high degree of computational efficiency. Substrate noise simulations were done using a 0.18 μm TSMC CMOS process technology using typical process parameters. A differential switched capacitor sample and hold circuit and a linear differential transconductor stage was used for the performance evaluation of this novel substrate model. Simulation results indicate a typical increase in Total Harmonic Distortion (THD) by atleast 6 dB due to the substrate noise effects, which corresponds to a performance loss by around 1-b precision. Also, the substrate noise effects are found to be proportional to the oversampling ratio (i.e., the digital clocking rate with respect to the input signal) and the net number of logic transitions at each register transfer instance in the mixed signal chip.

Noninvasive, low-noise, fast imaging of blood volume and deoxygenation changes in muscles using light-emitting diode continuous-wave imager

This article focuses on optimizing the signal to noise ratio (SNR) of a three-wavelength light-emitting diode (LED) near-infrared continuous-wave (cw) imager and its application to in vivo muscle metabolism measurement. The shot-noise limited SNR is derived and calculated to be 2×104 for the physiological blood concentrations of muscle. Aiming at shot-noise limited SNR performance and fast imaging, we utilize sample and hold circuits to reduce high-frequency noise. These circuits have also been designed to be parallel integrating, through which SNR of 2×103 and 2 Hz imaging acquisition rate have been achieved when the probe is placed on a muscle model. The noise corresponds to 2×10−4 optical density error, which suggests an in vitro resolution of 15. 4 nM blood volume and 46.8 nM deoxygenation changes. A 48 dB digital gain control circuit with 256 steps is employed to enlarge the dynamic range of the imager. We utilize cuff ischemia as a living model demonstration and its results are reported. The instrument is applied during exercise to measure the changes of blood volume and deoxygenation, which provides important information about muscle metabolism. We find that the primary source of noise encountered during exercise experiment is from the random motion of muscle. The results demonstrate that the LED cw imager is ideal for the noninvasive study of muscle metabolism.

Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration

An analog CMOS peak detect and hold (PDH) circuit, which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its high absolute accuracy, two or more PDHs can be used in parallel to serve as a data-driven analog memory for derandomization. The first experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35 μm CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.3 mW power dissipation, 250 mV/s droop rate, and negligible dead time. The use of such a high performance analog PDD can greatly relax the requirements on the digitization in multi-channel systems.

Ultrafast differential sample and hold using low-temperature-grown GaAs MSM for photonic A/D conversion

This letter demonstrates an ultrafast sample and hold circuit using optically triggered metal-semiconductor-metal switches made of low-temperature-grown GaAs for use in a photonic analog-to-digital conversion system. A differential configuration is incorporated to reduce feedthrough noise.

Discrete control for a computer hard disk by using a fractional order hold device

It is well known that the type of hold circuit used in a digital control scheme critically influences the position of the discrete-time zeros. Most digital control systems use a zero-order hold (ZOH). Nevertheless, there are more convenient alternatives to the use of a ZOH signal reconstruction device in certain digital control problems. A fractional order hold (FROH) circuit is proposed in the paper in order to manage a computer hard disk read-write head described as a second order system. Significant improvements in the transient performance of the closed-loop system are obtained with respect to the use of a ZOH when using a properly adjusted FROH device.

Simple vocal identification method of porpoise sonar signals using an acoustic data logger and a time depth recorder

Individual identification is needed for the standard behavioral observation. However, the vocal identification of cetacean sound is difficult even using an acoustic data logger attached to the animal, because it is hard to exclude the sounds from a nearby conspecific. This paper shows that simultaneous measurement of echolocation signals and the dive depth of a free-ranging finless porpoise (Neophocaena phocaenoides) enables vocal identification. Echolocation signals of a juvenile finless porpoise were observed with an acoustic data logger attached to the upper posterior side of the pectoral fin by a suction cup. The acoustic data logger had 4.8-kHz sampling frequency and recorded each event of pulse, processed by an amplitude peak hold circuit. Dive depth and swim speed of the porpoise were recorded by another data logger every 1 s. Surface reflection of echolocation signals was clearly detected during shallow dives less than 2 m in depth. The delay time of the reflected signal corresponded with the two-way transmission time from the animal dive depth to the surface. This shows that the signals were from the animal wearing the data loggers.

Comparison of Transient Performances in Adaptive Control for Different Hold Devices

In this paper, the transient performances in simple adaptive control problems are compared when several sampling and hold circuits of standard types are used. It was found that the most appropriate hold circuit is highly dependent on the kind of reference signal to be tracked. The interpretation is that the transient performances are dependent on the efficiency of the updating process of parametrical estimates related to the reference signal. Surprisingly, at a first glance, the use of a zero-order hold leads to better transient performances compared to the use of higher order devices.

A global passive sampling technique for high-speed switched-capacitor time-interleaved ADCs

In this paper, we present a passive sampling technique for time-interleaved switched capacitor analog-to-digital converters (ADCs). The purpose of the proposed sampling technique is to reduce the effect of delay skews between the sample and hold (SCH) circuits in the parallel channels, which limits the performance at high signal frequencies. If designed properly, the circuit can reduce the delay-skew related distortion by 10-20 dB compared to an architecture without a global input S/H circuit. Since no op amp needs to work at the full speed of the ADC, the circuit is suitable for high-speed and consumes less power than an architecture with an active input S/H circuit.

A programmable, low noise, multichannel ASIC for readout of pixelated amorphous silicon arrays

Pixelated amorphous silicon arrays used for detecting X-rays have a number of special requirements for the readout electronics. Because the pixel detector is a high-density array, custom integrated circuits are very desirable for reading out the column signals and addressing the rows of pixels to be read out. In practice, separate chips are used for readout and addressing. This paper discusses a custom integrated circuit for processing the analog column signals. The chip has 32 channels of low-noise integrators followed by sample and hold circuits which perform a correlated double sample. The chip has several programmable features including gain, bandwidth, and readout configuration.

Dual bridge 6 Gsample/s track and hold circuit inAlGaAs/GaAs/AlGaAs HEMT technology

A T&H circuit with a sampling rate of 6 Gsample/s has been experimentally demonstrated in AlGaAs/GaAs/AlGaAs HEMT technology. The circuit utilises a dual bridge topology suitable for interleaved ADC circuits, doubling the effective sampling rate with an insignificant increase in area compared to the previously reported solutions.

Radiation-hard hybrid superconducting pixel detector

Recently, a new position-sensitive cryogenic detector for out-of-magnetic-field high-energy particle tracking has been proposed. This consists of a semiconductive substrate to transduce the energy of particles in charge and of a current-driven Josephson-Tunnel Junction-based sample and hold circuit. The main interest in such a device consists in the extreme radiation hardness of the Josephson readout circuitry. Moreover, these circuits offer unique performances in terms of speed and power dissipation. Using radiation-hard semiconductive transducers the entire detector is expected to safely survive a dose of one Gigarad.

45.1: Analog Interface LSI for UXGA Color TFT‐LCDS

AbstractA Analog Interface LSI (AIF‐LSI) for UXGA (1600 × 1200)displays has been developed by using Bi‐CMOS process. AIF‐LSI operates on an analog signal processing for conventional CRT compatible interface without any additional circuits. By using this AIF‐LSI, The TFT(thin film transistor) LCD module can display with full color (more than 16million colors simultaneously). This AIF‐LSI consists of clamp circuit, sync‐comparator, γ‐correction, sample & hold circuit, selector‐circuit and data‐inversion circuit.

Partial scan design based on levellised combinational structure

To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. A ‘combinational structure’ has been developed to avoid the use of a sequential test generator. But test patterns shifted on the scan register have to be held for a sequential depth period upon the aid of the dedicated HOLD circuit. In this paper a new levellised structure is introduced aiming to exclude the need for an extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can be applied by scan shifting and then pulsing a system clock like the full scan, but with many fewer scan flip-flops. Experimental results show that some sequential circuits are levellised by just scanning self-loop flip-flops.

Hybrid superconducting pixel detector

A new position sensitive cryogenic detector for high energy particles based on Josephson Tunnel Junctions (JTJs) is proposed. This consists of a semiconductive substrate to transduce the energy of particles in charge and of a JTJ as a current driven sample and hold circuit. The possibility of coupling to high-speed Josephson logic families and the sensitivity to magnetic fields are also addressed.

A 3-V 5.4-mW BiCMOS track & hold circuit with sampling frequency up to 150 MHz

A track & hold circuit to be used in front of a high-speed analog-to-digital converter (ADC) is proposed. In order to achieve the required resolution with a single 3-V supply, a fully differential closed-loop architecture is used. The track & hold circuit processes a differential 1-Vpp output signal swing and achieves more than 8-b linearity with sampling frequency up to 150 MHz. In these conditions, the total power consumption is 5.4 mW from a single 3-V supply. The circuit has been realized in a 0.7 /spl mu/m BiCMOS technology, and its active area is about 0.15 mm/sup 2/.

Nuclear instrumentation for a soft X-ray detection system on a small satellite, CATSAT

Nuclear instrumentation has been designed and tested for a large field of view soft X-ray sensor utilizing Si avalanche photodiodes (APDs). The instrument will be launched on a low cost satellite mission in mid 1998. The mission's primary scientific objective is to determine the distance scale to the sources of cosmic gamma ray bursts by utilizing interstellar absorption effects observable in their X-ray emission at energies below 2 keV. The soft X-ray (SXR) sensor incorporates 7 identical panels, each with 16 APDs collectively collimated to a 1 steradian field of view. The SXR panels are radiatively cooled to -35 degrees C, and taken together, view a full hemisphere. The instrumentation for each of the sensors in the SXR detector includes a low noise, charge sensitive preamplifier/shaping amplifier and an analog electronics unit (AEU) containing a voltage amplifier, peak track and hold circuit, and threshold-timing logic. Each panel has an analog to digital interface (ADI) based on a field programmable gate array (FPGA), which controls the digitization of the event amplitudes, implements the in-flight calibration (IFC) for each APD, and coordinates the data output to and command input from the instrument CPU.