Capacitor matching insensitive algorithmic ADC requiring no calibrations

Abstract

A novel implementation of the algorithmic ADC is proposed in this paper. The ADC is based on an algorithmic 1.5-bit stage in which voltage multiplication is replaced by voltage addition. A floating voltage hold circuit is proposed which enables the accurate addition of signal voltages without requiring precision components. An experimental 12 bit 3.3 MS/s algorithmic ADC in 0.25 μm standard CMOS is described. It occupies 0.15 mm 2 of die area and dissipates 5.5 mW. The power and area FOMs are well below those previously reported for 1.5-bit stage algorithmic ADCs.