Abstract
In this paper, we present a passive sampling technique for time-interleaved switched capacitor analog-to-digital converters (ADCs). The purpose of the proposed sampling technique is to reduce the effect of delay skews between the sample and hold (SCH) circuits in the parallel channels, which limits the performance at high signal frequencies. If designed properly, the circuit can reduce the delay-skew related distortion by 10-20 dB compared to an architecture without a global input S/H circuit. Since no op amp needs to work at the full speed of the ADC, the circuit is suitable for high-speed and consumes less power than an architecture with an active input S/H circuit.
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