High Ge Content Research Articles

Germanium Atoms Exceed the Tetrahedral Coordination in MFI Zeolite.

Germanium is known to occupy tetrahedral sites by substituting silicon in germanosilicate zeolites. In this study, we present pioneering findings regarding the synthesis of zeolites with an MFI structure (GeMFI) incorporating a high germanium amount (16% Ge). Remarkably, the germanium atoms feature a slight electron deficiency with respect to GeO2, and the typical coordination number of 4, as usually reported for the germanosilicate zeolites, is exceeded, giving rise to Ge dimers in a double-bridge configuration. Notably, the compensation of the ammonium template is achieved not through fluorine ions in the [415262] cages of the framework, as conventionally considered, but rather through oxygen. The GeMFI zeolite with the high Ge content reported in this work demonstrated exceptional thermal and hydrothermal stability, surpassing up to 1050 °C, thanks to both the double-bridge configuration and the defect-free structure. The unexpected role of germanium in MFI zeolite challenges previous assumptions, representing a paradigm shift in the understanding of porous germanosilicate structures, paving the way for a reevaluation of their synthesis, hydrolysis, and potential applications.

Threading Dislocation Density Reduction in SiGe Strain Relaxed Buffer Layers through a Preexisting Dislocation Reservoir

Silicon germanium strain relaxed buffer layers (SRB) enable the integration of strained Si or strained Ge layers that can be used for improving CMOS devices with enhanced carrier mobilities, optoelectronics or emerging applications like qubit devices. Due to the lattice mismatch between Si and Ge, the formation of misfit dislocations during strain relaxation is inevitable. Misfit dislocations are accompanied by threading dislocations that penetrate the surface and possibly affect the device performance. A reduction of threading dislocation densities (TDD) with for example graded buffer layers [1] therefore has been subject of extensive research in the past and remains an active field today.In an earlier work we showed, that by using a backside deposition process [2],[3] - initially intended for controlling the wafer bowing - preexisting dislocations that are introduced at the edge of the wafer can fundamentally change the relaxation process of SiGe buffer layers.[4] Instead of rapid nucleation and multiplication of dislocations at single sites that lead to the formation of misfit dislocation bundles and pile-ups through blocking, the dislocations in the reservoir at the wafer edge can start gliding immediately upon reaching the Matthews and Blakeslee critical thickness [5] and form an evenly distributed dislocation network without pile-ups (Fig. 1a). With this method, the threading dislocation density of low strain layers (2% Ge) can be reduced by one order of magnitude.In this work, we analyze the influence of the backside approach on the crystal quality of strain relaxed buffer layers with higher Ge concentrations more relevant for industrial applications. SiGe buffer layers were grown using a high temperature (>820 °C), atmospheric CVD process using SiH2Cl2 and GeCl4 as precursor gases on commercial polished 300 mm Si wafers and substrates that received a backside deposition prior to the front side buffer growth. For strain relaxed buffers with constant composition the largest relative TDD reduction is observed at low Ge concentrations (one order of magnitude at 2% Ge). The TDD reduction becomes more and more ineffective towards higher Ge concentrations (Fig. 1b) which is attributed to increased spontaneous nucleation of misfit dislocation half-loops. At 10% Ge there is no significant improvement observed. However, when moving from constant composition buffers to graded buffers to 25% or 70% Ge, the TDD is still reduced by approximately 1 × 105 cm-2 to 1.5 × 105 cm-2 and 5 × 105 cm-2, respectively (Fig. 1c). This is attributed to the removal of misfit dislocation bundles and pile-ups, that would block gliding dislocations from efficiently relaxing strain by trapping them and therefore increasing the need for nucleation of additional loops that increase the TDD. The absence of dislocation pile-ups also improves the surface quality (visual haze) of the SRB (Fig. 1d,e) as inhomogeneities in the dislocation network caused by misfit dislocation bundles that would lead to deep troughs in the crosshatch pattern are reduced. This is also reflected in the FWHM from rocking curves measured by HRXRD which is reduced by 60% for SRB with high Ge concentrations indicating a vastly improved crystal quality.In conclusion, this work highlights, that the drastically changed relaxation mechanism in the early stage of buffer growth by introducing a dislocation reservoir at the edge of the wafer has lasting consequences for the crystal quality of SRB even at high Ge concentrations. The prevention of dislocation bundle formation leads to a reduction of pile-up density, TDD, surface roughness and an overall improved crystal quality. The presented approach opens up the opportunity for a further reduction of the TDD that is necessary for future industrial applications of SiGe SRB.[1] E. A. Fitzgerald, Y.-H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J. Michel, Y.-J. Mii, and B. E. Weir, Appl. Phys. Lett. 59, 811 (1991).[2] P. Storck and M. Vorderwestner, US2009236696, (2009).[3] G. Kozlowski, O. Fursenko, P. Zaumseil, T. Schroeder, M. Vorderwestner, and P. Storck, ECS Transactions 50, 613 (2013).[4] L. Becker, P. Storck, T. Schulz, M. H. Zoellner, L. Di Gaspare, F. Rovaris, A. Marzegalli, F. Montalenti, M. de Seta, G. Capellini, G. Schwalb, T. Schroeder, and M. Albrecht, J. Appl. Phys. 128, 215305 (2020).[5] J. W. Matthews and A. E. Blakeslee, Journal of Crystal Growth 29, 273 (1975). Figure 1

An Assessment of the Lateral Selective Etching, with HCl, of High Versus Low Ge Content SiGe Layers

We have evaluated the feasibility of performing, with gaseous HCl, a lateral selective etching of high versus low Ge content SiGe layers. Such a know-how might be useful to fabricate, besides Complementary Field Effect Transistors, other types of devices relying on stacked nanosheets and multiple selective etchings such as 3D Resistive or Oxyde Random Access Memories (for In-Memory Computing).To that end, we have grown {20 to 25 nm thick Si / ~ 12-15 nm thick Si0.8Ge0.2 or Si0.75Ge0.25 / ~ 11-14 nm thick Si0.5Ge0.5} multilayers on SOI substrates. After a low temperature capping with SiN, such stacks were patterned into regular arrays of square mesas or lines with a stop on the buried oxide, to laterally have access to the layers of interest. The temperature used, in our 300 mm Reduced Pressure - Chemical Vapor Deposition chamber, to grow such stacks was 550°C. Meanwhile, the in-situ HCl etch temperature was always 500°C. The aim of such low process temperatures was to minimize the thermal budget multilayers were submitted to, in order to minimize elastic relaxation and avoid plastic relaxation while still having reasonable growth and etch rates. The overall compressive strain was indeed high in such stacks given the number, individual thicknesses and Ge concentrations of SiGe layers. Multilayers grown at 550°C, 20 Torr with (i) a SiH2Cl2 + GeH4 chemistry for Si0.5Ge0.5, (ii) a Si2H6 +GeH4 chemistry for Si0.75Ge0.25 or Si0.8Ge0.2 and (iii) pure Si2H6 for Si were in some places defective, with the presence on the surface of islands. Such defects were likely due to Si2H6 mass-flows which were too large, resulting in gas phase nucleation and, in some places, the formation of defects that increased in size as growth happened. We thus proceeded differently. Instead of Si2H6 + GeH4, we have used a SiH4 + GeH4 chemistry for the epitaxy of SiGe 20% or 25% layers. We succeeded in having reasonable SiGe 20% and 25% growth rates at 550°C, 20 Torr, which was not a given with that chemistry. We also showed that a x/(1-x) = 2.81*F(GeH4)/F(SiH4) relationship perfectly accounted for the almost linear increase of the Ge concentration x with the F(GeH4)/F(SiH4) mass-flow ratio. We otherwise reduced the Si2H6 mass-flow and added HCl to minimize gas phase nucleation and suppress the formation of amorphous inclusions in the Si layers. The linear dependency of the 550°C, 20 Torr Si growth rate on the Si2H6 and HCl mass-flows was modelled with the following phenomenological relationship: Si Growth Rate (nm min.-1) = 3260*F(Si2H6)/F(H2) – 1070*F(HCl)/F(H2).We then determined, at 500°C, 600 Torr, the (001) blanket HCl etch rates of SiGe 30% and 40%: 1.37 and 5.28 nm min.-1. Based on such data, we should have the following SiGe 50%, 25% and 20% etch rates: 20.0, 0.70 and 0.36 nm min.-1, respectively. Meanwhile, the pure Si etch rate should be negligible: 0.025 nm min.-1 only. Should we then define theoretical selectivities as being ratios between (i) SiGe 50% and (ii) SiGe 25%, SiGe 20% or pure Si blanket (001) etch rates, we would obtain promising selectivities (29, 56 and 800) when laterally etching of SiGe 50% versus SiGe 25% SiGe 20% and Si.We then switched over to patterned wafers. The lateral selective etching of Si0.5Ge0.5 versus Si0.8Ge0.2 (and Si) was feasible. The following features were highlighted: (i) Si0.5Ge0.5 lateral etch rates along the <110> directions were much smaller than in the [001] direction and (ii) because of micro-loading, lateral etch rates were definitely higher for squares than for lines (0.9 - 1.1 nm min.-1 for lines, to be compared with 1.7 – 2.1 nm min.-1 for squares). Meanwhile, the lateral selective etching of Si0.5Ge0.5 versus Si0.75Ge0.25 was far from being perfect, with much higher Si0.5Ge0.5 etch rates and a significant Si0.75Ge0.25 recessing at tunnel entrances (see Figure 1). Si0.75Ge0.25 floors and ceilings were otherwise far more etched and thus tilted than Si0.8Ge0.2 ones. Inserting very thin Si spacers between Si0.5Ge0.5 cores and Si0.75Ge0.25 claddings partly solved those issues, with no recessing and lesser etchings at the entry points of tunnels, then (see Figure 2). Figure 1

(Invited) Low Temperature SiGe:B Epitaxy for Next-Generation Logic Devices

Epitaxy at low temperatures (< 400°C) will be essential to enable advanced node CMOS logic architectures such as gate-all-around and complementary field effect transistors [1]. Beyond complying with the related thermal budget limitations, the non-thermal-equilibrium conditions drastically increase the attainable active doping level in epitaxially grown source/drain (S/D) materials. This is a crucial benefit for minimizing the contact resistivity ρC between S/D and contact metal, which, with shrinking device dimensions, becomes the major contributor to parasitic resistance [1] . Another strategy for ρC reduction in p-type S/D is reducing the Schottky barrier height (SBH), for which SiGe:B layers with very high Ge content, up to Ge:B, have been considered [2]. In this work, we report on achieving unprecedented active doping NA = 4.2×1021 cm-3 (Hall Scattering Factor [HSF] = 1) with Ge contents as high as 80% - a dual benefit for ρC reduction. In this context, we furthermore demonstrate two in-line methods for non-contact and non-destructive characterization of composition and electrical parameters in highly doped SiGe:B thin films.We first discuss the general benefits of low temperature epitaxy, highlighting the improvements in attainable active doping and layer resistivity depicted inFig. 1. We then demonstrate how the high concentration of dopants enables metrology techniques for characterization of composition and electrical parameters of low-temperature SiGe:B thin films, that were so far mainly used for thicker layers or different material systems: Wavelength-dispersive x-ray fluorescence (WDXRF) and Fourier-transform infrared spectroscopy (FTIR). Fig. 2 demonstrates how the WDXRF detection of Ge was calibrated with SiGe films and transferred to SiGe:B. Fig. 3 demonstrates the application of the WDXRF for LT-SiGe:B films, and the direct detection of B concentration by XRF. In Fig. 4, the results of FTIR measurements based on a Drude dispersion model approach are shown for layer resistivity and NA. Systematic differences between the active doping are explained by respective assumptions of HSF equal to 1 and the effective hole mass as 0.37me. FTIR shows better agreement with the substitutional B concentration as extracted from x-ray diffraction, calculated from a three-component Vegard’s law assuming aB = 3.806 Å, as displayed in Fig. 5.We proceed to demonstrate the usefulness of WDXRF and FTIR in process development. We previously reported on low-temperature selective epitaxial growth of SiGe:B with Ge = 60%, NA = 2.9×1021 cm-3 (Hall, HSF=1) with resulting contact resistivity below 5×10-10 Ω-cm2 measured by ladder transmission line method [3 ,4], based on conventional precursors. In a fundamental change to the process, we introduced novel precursor material. Fig. 6 demonstrates, for a similar Ge content around 70%, the drastic increase of total incorporated B per supplied B precursor when using the new precursor configuration by use of WDXRF. The reduction in ‘apparent’ Ge (strain compensated by B) content, reduction in attainable resistivity and increase in NA measured by FTIR prove enhanced substitutional (active) Boron concentration. The NA as of Hall measurement is also drastically increased in absolute value, but in saturation, which may be explained by the HSF increasing for high concentrations of B [5]. The newly developed process exhibits drastic enhancement of achievable NA in conjunction with increased Ge concentration of the layer up to 80% compared to previously reported process types [1,3 ,4], as shown in Fig. 7. Fig. 8 displays the relation between NA and hole mobility (HSF=1) for the process types involving the new precursor, and conventional precursors, proving that electrical conductivity is generally improved with introduction of the new precursor.Reciprocal space maps for two ~15nm thick layers with Ge = 80% in Fig. 9 prove the transition from initial signs of relaxation to a fully strained layer by doubling the B precursor flow, while SIMS results show a 1.7x increase in incorporated B, highlighting the strain compensation effect of B. A transmission electron micrograph demonstrates perfect quality of the 15nm thick SiGe:B thin film, and defect-free substrate-to-film interface.Finally, fully selective growth on a full patterned wafer with a Si/SiNx/SiO2 structure is depicted in a transmission electron micrograph in Fig. 10.[1] C. Porret et al., 2022 IEDM, 34.1.1-34.1.4, [2] O. Gluschenkov et al., 2016 IEDM, 17.2.1-17.2.4,[3] R. Khazaka et al., 2022 ECS Trans. 109 87 [4] G. Zheng et al., 2023 VLSI, 1-2 [5] F. Severac et al., J. Appl. Phys. 105, 043711 (2009) Figure 1

(Invited) Graded Index Silicon Germanium Photonics Circuits in the Mid-Infrared

Mid-infrared (mid-IR) spectroscopy can be used to identify chemical and biological substances. Indeed, most molecules absorb light at specific wavelengths in the mid-infrared (mid-IR). Mid-IR photonic circuits on silicon chips have recently gained a lot of attention. Indeed, they can provide high-performance with a low power consumption, while being cheap, compact, and light. Germanium (Ge) and silicon-germanium (SiGe) alloys with a high Ge concentration are particularly interesting because of the wide transparency window of Ge extending up to 15 µm. It has been demonstrated for a few years now that a Ge-rich graded SiGe platform relying on a graded SiGe layer epitaxially grown on a Si substrate can be used as a photonics platform for mid-IR operation in a wide spectral range.In this invited talk, recent developments concerning graded SiGe photonic integrated circuits will be presented. First, passive devices will be reviewed. It will be shown that graded-SiGe waveguides can be used in an unprecedented spectral range, e.g. up to 11 µm. Mach Zehnder interferometers, resonators and integrated Fourier transform spectrometers will be discussed. Then, a large bandwidth light source based on non-linear optical effects in SiGe waveguides [1] will be presented, together with results on integrated mid-IR optoelectronic modulators [2, 3]. Tunable electro-optical frequency-comb generation around 8 µm wavelength based on such integrated modulators will also be discussed [4]. Finally, the recent scale-up of this platform will be shown, with the first demonstration of low-loss mid-infrared waveguides fabricated on a Ge-rich SiGe strain-relaxed buffer grown on an industrial-scale 200 mm wafer [5].Acknowledgment:This work was co-funded by ANR Light-up Project (ANR-19-CE24-0002-01) and by European Union (ERC, Electrophot,101097569). This work was partly supported by the French RENATECH network.

Advanced SiGe:B Raised Sources and Drains for p-type FD-SOI MOSFETs

We have evaluated the feasability of selectively growing (at 600°C-700°C, 20 Torr and with a SiH2Cl2 + GeH4 + B2H6 + HCl chemistry) SiGe:B Raised Sources and Drains on each side of PMOS FD-SOI devices with a vertical Ge concentration gradient. The reason was twofold : (i) inject meaningful amounts of uniaxial compressive strain and boost hole mobility thanks to really high Ge concentrations (50%) in layers on each side of the channel and (ii) benefit from SiGe:B 20% to 30% layers on top, that are easier to germano-salicide, for instance with Ni or NiPt. As the diborane flow increased, we had, whatever the Ge concentration (20%, 30% or 50%), (i) sub-linear SiGe:B growth rate increases (from +14% up to + 23%) and (ii) linear decreases of the “apparent” Ge concentration from X-Ray Diffraction (XRD), as shown in Figures 1a and 1b. They were due to (i) a catalysis of H/Cl desorption by B adatoms and (ii) compressive strain compensation by small size B atoms, respectively. The resulting substitutional B concentrations increased almost linearly with the B2H6 mass-flow. The slopes of those increases were steeper and B concentrations systematically higher for higher Ge contents, however (at most 2.2x1020 cm-3 for 50% of Ge), as illustrated in Figure 1c. We otherwise showed, for Si0.7Ge0.3:B layers, that the Ge atomic concentration was steady as the B2H6 mass-flow increased. Atomic, substitutional and ionized B concentrations (from Secondary Ions Mass Spectrometry, XRD and Hall effect measurements) were the same for the lowest diborane flow probed (e.g. 7x1019 cm-3). For a medium flow, atomic and substitutional B concentrations were equal (e.g. 1.4x1020 cm-3), while the ionized B concentration was ~80% of it. Discrepancies were the highest for the highest diborane flow probed, with substitutional and ionized B concentrations ~80% and ~60% the atomic B concentration of 2.3x1020 cm-3, then (Figure 1d). The specifics of SiGe:B Selective Epitaxial Growth (SEG) in sources and drains regions on each side of FD-SOI devices (Figure 2) were then described, such as (i) loading effects, because of the presence of dielectrics, resulting in significant growth rate increases (x1.5 - x1.7), together with slight Ge and B concentrations increases that might impact the layer quality on patterned wafers, (ii) facet formation, (iii) the importance of proper surface preparation prior to epitaxy and of tight SiN hard masks on top of poly-Si gates, (iv) the strain loss happening upon germano-salicidation and so on. Growing a thin Si(:B) cap on SiGe:B is another way of obtaining uniform and stable metallic contacts. This is why we have studied the capping, with pure Si, of SiGe 20% or 30% layers. As growth had to be conducted, for the SEG of Si with a chlorinated chemistry, at temperatures significantly higher than that of SiGe (750°C, typically, to be compared with 700°C for SiGe 20% and 650°C only for SiGe 30%), we have quantified the impact of using temperature ramping-ups with SiH2Cl2 + HCl flowing into the growing chamber. The purpose of such active ramps was to avoid elastic strain relaxation, e.g. the formation of SiGe surface undulations that would happen with temperature ramping-ups under H2 only. Superior quality 2D SiGe / Si stacks were then obtained, as shown by X-Ray Reflectivity and XRD. Energy Dispersive X-ray maps of such stacks enabled us to quantify loading effects on patterned wafers. SiGe growth rates in small, recessed windows were 1.5 times (SiGe 30%) – 1.8 times higher (SiGe 20%) than on bulk, blanket Si. Meanwhile, Ge concentrations were 2% to 3% higher. Finally, Si growth rates were lower than bulk, most probably because of the presence of thick buried oxide layers on those patterned wafers that impacted the effective surface temperature during growth. Figure 1

Piezo Electric Properties of Epitaxial SiGe

Strain sensors are highly demanded in industrial fields such as for precise torque control of electrical motors as well as for manipulators of industrial robots to handle soft materials to recognize the state of grabbed objects(1,2). Polycrystalline-Si based membrane sensors have great potential for downscaled and monolithic integration because their small occupying area enables high density arrays with a relatively large physical change for high sensitivity. However, by downscaling, fluctuations of the device properties, due to variation of polycrystalline grain size, become more pronounced, which strongly reduces the sensing reliability of the devices. This fluctuation could be improved by switching from polycrystalline to single crystal material. In last three decades, polycrystalline Si has been widely used as an effective material for highly sensitive strain sensors. In this study, we evaluate piezo resistivity of epitaxial SiGe to assess its potential and feasibility for strain sensor applications.The piezo resistivity of epitaxial SiGe layers is investigated based on using the gauge factor (GF). 100 nm-thick, B-doped SiGe with 10, 20 and 30% Ge content is pseudomorphically grown using reduced pressure chemical vapor deposition on n-type Si(001). B concentrations are varied from ~1×1017 to ~1×1019cm-3 verified by SIMS measurements. The deposited SiGe is patterned by photolithography and dry etching to form a 16µm wide and 300µm long stripe as schematically shown in Fig. 1 (a). Afterwards the SiGe is passivated by 200nm thick SiO2 and windows for metal contact pads are opened. In order to ensure ohmic contact for the metal contact pads a layer stack consisting of Al/~30nm-thick Ni/Ni silicide/~50nm-thick ~1×1019cm-3 B-doped Si was deposited onto the SiGe layer as schematically shown in Fig. 1 (b). Then, the substrate is thinned down to 200µm and diced to 2×2cm2 square. The test structure is located at the center of the diced wafer. In order to prevent unintended relaxation of the deposited SiGe layer, temperatures for following post-epitaxy processes are limited to below 550°C.In order to measure the piezo resistivity, the resistance is determined using four-terminal measurement with bending the sample by four-point bending method as shown in Fig. 2(3). By the wafer bending, uniaxial compressive strain along the 300µm direction is externally applied. The GF is estimated by slope of relative resistivity as function of induced strain.In Fig. 3, GFs of the SiGe as function of resistivity with 10, 20 and 30% Ge content are summarized. For this experiment, SiGe growth is performed at 600°C for all samples. In the case of higher resistivity, (i.e. sample with lower B concentration), higher GF is observed. Within the same resistivity, slightly higher GF is obtained for the SiGe with higher Ge content. A possible interpretation would be, the GF is related to hole mobility. The hole mobility enhancement is expected by increased Ge content in the SiGe and externally introduced additional uniaxial compressive strain along current flow direction(4). In the case of higher carrier concentration, the hole mobility enhancement is less pronounced due to scattering. However, further investigation is required to understand the mechanism behind.Next, in order to discuss influence of the SiGe growth conditions on the GF, GF of Si0.8Ge0.2 grown different growth temperature is compared. Resistivity of all samples is 6×10-1Ωcm. In the parallel experiment, no plastic strain relaxations of the SiGe are confirmed for the process conditions used for this experiment. It seems even though Ge concentration, thickness and carrier concentrations are the same, electrical property of the deposited SiGe is influenced by changing the growth temperature.In order to investigate a possible reason of the influence of the SiGe growth condition on the GF, C-V characteristics of SiGe are evaluated by fabricating MOS structures. In order to reduce interface state density, a 10 nm thick Si cap layer is deposited on the SiGe layers to prevent Ge oxide formation at the oxide Si interface. The evaluation of electrical interface and bulk parameters by means of simultaneously measured high- and low frequency MOS C-V characteristics in non-steady state non-equilibrium indicate that lower density of recombination-generation centers are existing for the SiGe grown at lower temperature. Therefore, higher crystal quality is confirmed for the Si0.8Ge0.2 layer grown at lower temperature.These results shown here gives prospect for tuning of SiGe based piezo resistivity sensors.References(1) H. Liu et al., Nanomachines 8 10, 304 (2017)(2) M. Amjadi et al., Adv. Funct. Mater. 26 (11), 1678 (2016)(3) N. Inomata et al., Sens. Act. A, 346 16 113823 (2022)(4) M.V. Fischetti et al. J. Appl. Phys. 80, 2234 (1996) Figure 1

Ultra-Low Temperature Epitaxy of Ge-Rich Nanosheets on SOI for Reconfigurable Transistor Applications

Implementing only tens of nanometer-thin Ge and Ge-rich SiGe nanosheets on SOI is expected to boost performance metrics of next-generation electronic devices, such as reconfigurable field effect transistors [1]. However, an inherent lattice mismatch between Ge and Si drastically limits the thickness of high-quality Ge layers on Si to a few monolayers, i.e., far too thin for practical nanosheet device applications. Thus, to date, many prototype Ge-rich nanoelectronics device concepts are based on nanowires' vapor-liquid-solid (VLS) growth. Since these nanowires grow on untypical (111) substrates and in a vertical manner, they need to be picked and placed onto Si(001) substrates: A serial process and, thus, barely scalable. Therefore, whenever two-dimensional nanosheets of a material are available, they provide distinct advantages with respect to the scalability of the device integration. Here, we show that pure Ge and SiGe alloyed nanowires can be formed top-down from nanosheets. We show that devices from nanowires based on Ge on SOI nanosheets have excellent quality and can outperform other material platforms, such as VLS nanowires or devices based on GeOI substrates, thereby enabling extended device functionalities [2].For high Ge contents and typical Ge growth temperature above 500°C, the achievable thickness of pseudomorphic, defect-free (Si)Ge epilayers is just a couple of monolayers if grown directly on Si(001) substrates [3,4]. Above this thickness, the inherent strain between the layer and SOI substrate leads to harmful plastic or elastic relaxation under common growth conditions.We depart from established (Si)Ge epitaxy temperatures of ≥500°C and employ molecular beam epitaxy (MBE) growth at ultra-low temperatures (ULT), ranging from 100°C to 350°C [5,6]. We show that the lowered surface kinetics leads to a pronounced layer supersaturation, allowing us to access layer thicknesses about an order of magnitude larger than previously reported values. Also, in contrast with previous results for ULT epitaxy [7], we do not observe layer amorphization even for growth at 100°C. Here, we highlight that pristine growth pressures deep in the ultra-high vacuum range (≤10-10 mbar) are crucial to keep the density of unwanted impurities in the (Si)Ge layers to a minimum and, thus, enable excellent electrical and optical properties of the grown heterostructures. These low growth pressures are particularly important in ULT growth since the low thermal budget impedes the efficient desorption of residual gas molecules from the substrate.We further show the fabrication of nanosheet transistors based on fully strained, defect-free (Si)Ge epilayers grown directly on SOI substrates [2,8,9]. For these devices, properties like thickness, SiGe(Sn) content, barrier material, and doping can be conveniently tuned during the epitaxy process beyond past limitations. We demonstrate that these nanosheets are a highly scalable platform for emerging devices, such as reconfigurable transistors with excellent performance [2,8,9] and highly symmetric n- and p-type transistor characteristics. Notably, the ULT-grown nanolayers withstand high-temperature device fabrication steps such as SiO2 formation and Al-SiGe exchange [2,8,9].

Substrate induced composition change during Ge2Sb2Te5 atomic layer deposition and study of initial reactions on SiO2 surface

Ge2Sb2Te5 (GST) is a well-known phase change material used in nonvolatile memory devices, photonics, and nonvolatile displays. This study investigates the impact of precursor sequence during atomic layer deposition (ALD) of GST from GeCl2.C4H8O2, SbCl3, and Te[(CH3)3Si]2 on Si/SiO2 substrates, focusing on growth per cycle, morphology, and composition along with initial precursor reactions on the substrate. We found that while thick layers approach stoichiometric Ge2Sb2Te5, a Ge-rich interfacial layer is initially formed, regardless of the binary ALD sequence used to start the deposition (GeTe vs Sb2Te3). Starting the ALD process with the GeTe-Sb2Te3 sequence results in a higher Ge content near the GST/SiO2 interface compared to the Sb2Te3-GeTe sequence. To understand these phenomena, we examine the initial precursor reactions on the SiO2 substrate by total reflection x-ray fluorescence spectrometry. The analysis reveals that SbCl3 exhibits lower reactivity with the SiO2 substrate than GeCl2.C4H8O2, and not all Ge adspecies react with the Te[(CH3)3Si]2 precursors. Additionally, the impact of the initial SiO2 surface on deposition extends over several ALD cycles, as the SiO2 surface only gradually gets covered by GST due to island growth. These processes contribute to the formation of a Ge-rich GST layer at the interface, irrespective of the precursor pulse sequence. These insights from the study may contribute to optimizing the initial deposition stages of GST and other ternary ALD processes to enable better composition control and enhanced device performance.

Tracing fluid signature and metal mobility in complex orogens: insights from Pb-Zn mineralization in the Pyrenean Axial Zone

AbstractOrogenic processes encompass a complex interplay of deformation and metamorphic events, which can impact the formation of ore deposits to various degrees. However, distinguishing fluid signatures from orogenic versus post-orogenic events presents a significant challenge due to the scarcity of robust geochemical indicators that remain unaffected during multiple post-mineral reworking events. This study carefully examines the properties and chemistry of primary and secondary fluid inclusions (FIs), identifying distinct signatures of two fluid populations linked to different styles of Pb-Zn mineralization in the Pyrenean Axial Zone (PAZ) of Southern-France/Northern-Iberia: These included late-Carboniferous stratabound epigenetic Pb-Zn deposits and Mesozoic crosscutting Pb-Zn(-Ge) vein systems. Population (I) is identified in primary and secondary FIs in a few crosscutting Pb-Zn veins and constitutes a minor component in stratabound epigenetic bodies. It exhibits Na-dominated low to intermediate salinity (&lt; 20 wt% NaCl eq.), intermediate temperatures (200–350 °C), abundant CO2-rich FIs and shows low homogeneous Cl/Br molar ratios. These characteristics are consistent with a metamorphic origin of the fluids, associated with Late-Variscan metamorphism. Population (II) is commonly observed in the crosscutting vein systems where it occurs as primary and pseudosecondary FIs, as well as in stratabound epigenetic bodies where it represents the main fluid component of secondary FIs. Population (II) is Ca-dominated with intermediate to high salinity (15–35 wt% NaCl eq.), relatively low temperature (&lt; 200 °C), and shows high Cl/Br molar ratios with significant variations. This last characteristic is typical of mixing of at least two fluids, one with a probable low Cl/Br molar ratio at shallow crustal levels and another with high Cl/Br molar ratio at deeper levels. Characteristics of population (II) are consistent with a fluid of basinal origin that interacted with the basement while circulating in the Pyrenees during the Mesozoic, although a Pyrenean-Alpine age cannot be excluded. Locally, in sphalerite-hosted secondary FIs that form trails in the crosscutting veins, we find evidence of high Ge concentrations (up to few 1000s ppm), which correlate with anomalous Pb and Tl concentrations. Very high metal concentrations (up to 1–2 wt% Pb, Zn), which are inversely proportional to Cl/Br molar ratios, are found in FIs mainly within veins hosted in deep-seated high-grade metamorphic rocks. Based on a compilation of fluid data from the literature, a first-order correlation can be deduced between the metamorphic grade of the rocks hosting the mineralization and the Pb and Zn content in the FIs. Early stratabound orebodies are considered likely sources of metal for the development of the late crosscutting vein mineralization. This study demonstrates the significance and complexity of orogen-scale fluid circulation and supports the importance of pre-existing metal enrichment in the crust, especially in high-grade metamorphic rocks as a prerequisite for the formation of Pb-Zn veins in complex multi-stage orogens.

Structural order and disorder within novel antiferromagnetic RCrxGa3-yGey and R4Cr1-xGa12-yGey intermetallic compounds (R = Tb, Dy)

Single crystals of intermetallic phases RCrxGa3−yGey (R = Tb, Dy; x = 0.19–0.23, y = 0–0.4) and R4Cr1−xGa12−yGey (R = Tb, Dy; x = 0–0.13, y = 3–4) were grown from Ga flux ensuring the absence of magnetic impurities. The X-ray diffraction experiments revealed that the compounds belong to the family of filled AuCu3-type gallides. The compounds are formed upon the insertion of Cr atoms into E6 octahedral voids (E = Ga/Ge), which can occur in either disordered (RCrxGa3-yGey) or ordered (R4Cr1-xGa12-yGey) fashion. The unique feature of the obtained compounds is the strong correlation between the level of Ge doping and the Cr concentration in the phases, which allows one to control both the structural and magnetic ordering. At low Ge concentration, the cubic RCrxGa3-yGey phases form, which then experience tetragonal distortion upon the increase in the Ge content, and the cubic R4Cr1-xGa12-yGey 2×2×2 superstructures are formed at even higher Ge concentrations. The X-ray diffraction analysis also showed a presence of structural defects in the phases, which are caused by different size of empty E6 and filled CrE6 octahedra. Magnetic measurements of the single crystals of the cubic phases reveal antiferromagnetic ordering of the rare earth sublattice with the Neel temperatures decreasing upon Ge doping from 22 K for RCrxGa3 to 10 K for R4Cr1−xGa12−yGey. The Ge doping causes gradual decrease in the strength of antiferromagnetic R-R interactions ultimately leading to noncollinear magnetic structure in the superstructure R4Cr1−xGa12−yGey phases.

An Assessment of the Lateral Selective Etching, with HCl, of High Versus Low Ge Content SiGe Layers

We have evaluated the feasibility of selectively etching, with gaseous HCl, high versus low Ge content SiGe layers. To that end, we have grown {20 to 25 nm thick Si / ~ 12-15 nm thick Si0.8Ge0.2 or Si0.75Ge0.25 / ~ 11-14 nm thick Si0.5Ge0.5} multilayers on SOI substrates. After a low temperature capping with SiN, such stacks were patterned into regular arrays of square mesas or lines with a stop on the buried oxide, to laterally etch the layers of interest. We first determined, at 500°C, 600 Torr, the (001) blanket HCl etch rates of SiGe 30% and 40%: 1.4 and 5.3 nm min.-1. We then switched over to patterned wafers. The lateral selective etching of Si0.5Ge0.5 versus Si0.8Ge0.2 (and Si) was feasible and the following features highlighted: (i) Si0.5Ge0.5 lateral etch rates along the <110> directions were much smaller than in the vertical [001] direction and (ii) because of micro-loading, lateral etch rates were definitely higher for squares than for lines (0.9-1.1 nm min.-1 for lines, to be compared with 1.7–2.1 nm min.-1 for squares). Meanwhile, the lateral selective etching of Si0.5Ge0.5 versus Si0.75Ge0.25 was far from being perfect, with much higher Si0.5Ge0.5 etch rates and a significant Si0.75Ge0.25 recessing at tunnel entrances. Si0.75Ge0.25 floors and ceilings were otherwise far more etched and thus tilted than Si0.8Ge0.2 ones. Inserting very thin Si spacers between Si0.5Ge0.5 cores and Si0.75Ge0.25 claddings partly solved those issues, with no recessing and lesser etchings at the entry points of tunnels.

Advanced SiGe:B Raised Sources and Drains for p-type FD-SOI MOSFETs

We have evaluated the feasability of selectively growing, with a chlorinated chemistry, 20 to 30 nm thick SiGe:B Raised Sources and Drains with Ge concentration gradients (from 50% down to 20%-30%, typically) on each side of FD-SOI transistors. The motivation was twofold: (i) inject meaningful amounts of compressive strain in the channel of p-type MOS devices thanks to high Ge concentrations in layers sitting in the same plane than Si or SiGe channels and (ii) benefit from lower Ge concentration SiGe layers on top that are easier to germano-silicide. Growing a thin Si(:B) cap on SiGe:B otherwise yields more uniform and stable contacts. We have thus studied the Si capping of SiGe 20% or 30% layers. As growth has to be conducted, for Si, at temperatures significantly higher than that of SiGe (750°C, to be compared with 700°C for SiGe 20% and 650°C for SiGe 30%, typically), we have quantified the impact of using temperature ramping-ups with SiH2Cl2 + HCl flowing into the growing chamber. The purpose of such active ramps was to prevent elastic strain relaxation, e.g. the formation of SiGe surface undulations that would happen with temperature ramps under H2 only.

Germanium distribution in Mississippi Valley-Type systems from sulfide deposition to oxidative weathering: A perspective from Fule Pb-Zn(-Ge) deposit, South China

Abstract Germanium (Ge) is a critical raw material for emerging high-tech and green industries, resulting in considerable recent interest in understanding its distribution and geochemical behavior in ore deposits. In this contribution, the distribution of Ge and related trace elements in the Fule Pb-Zn(-Ge) deposit, South China, is investigated to reveal the distribution of Ge in the hydrothermal ores and during sulfide weathering, using multiple microanalytical techniques, including scanning electron microscopy, electron probe microanalysis and laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS). In the Fule MVT deposit, sphalerite (ZnS) is the most significant Ge-carrier relative to other sulfides, though the five recognized textural types of sphalerite display progressive depletion in Ge from the first sphalerite generation to the late one. In the early stage, sphalerite with fine-grained chalcopyrite inclusions has the highest Ge concentrations, probably accounting for a significant proportion of the total Ge. We interpret that high Ge concentrations in the early sphalerite may be attributable to high Cu activity in the mineralizing fluids. During oxidative weathering, Ge was redistributed from its original host, sphalerite, to the weathering product willemite (Zn2SiO4) rather than smithsonite (ZnCO3), with high levels of Ge (up to 448 μg/g) present in the willemite. The formation of abundant willemite largely prevents the dispersion of Ge during weathering. In principle, willemite-hosted Ge should be fully recoverable, and the Zn-silicate ores may, therefore, be a potential target to meet future demand. This study provides new information on how Ge behaves from sulfide- to weathering-stage in MVT systems, which directly impacts Ge mobility and deportment changes and the development of metal-lurgical strategies for Ge recovery.

High-Quality Ge-Rich Nanosheets on Silicon on Insulator Substrates Based on Ultra-Low Temperature Epitaxy

Ge and Ge-rich SiGe channel materials are expected to enhance performance in next-generation electronic devices, such as e.g. reconfigurable field effect transistors [1]. However, an inherent lattice mismatch exists between Ge and Si of about 4%. Ge layers on Si grow under compressive in-plane strain, drastically limiting the thickness of high-quality Ge layers on Si to a few monolayers, i.e., far too thin for practical device applications.In principle, vertically grown nanowires grown by vapor-liquid-solid growth (VLS) can be used to overcome these limitations as their small footprint can mitigate the strain. That is why, to date, basically all Ge-rich nanoelectronics device concepts are based on VLS nanowires.However, for device fabrication, the nanowires grown on untypical (111) substrates need to be picked and placed onto Si(001) substrates, which is a serial process and, thus, barely scalable.Thus, whenever two-dimensional nanosheets of a material are available, they provide distinct advantages with respect to device integration. In this context, pure Ge and SiGe alloyed nanowires formed from through top-down lithography from nanosheets would enable extended device functionalities.The problem is that for high Ge contents, the achievable thickness of pseudomorphic, defect-free (Si)Ge epilayers is just a couple of monolayers if grown directly on Si(001) substrates [2] as the inherent strain between the layer and substrate leads to harmful plastic or elastic relaxation under common growth conditions. Thus, using conventional epitaxy, the attainable defect-free SiGe/Si layer thicknesses are typically far from usable in electronic transport devices.Therefore, we depart from established (Si)Ge epitaxy temperatures of ≥500°C and employ molecular beam epitaxy (MBE) growth at ultra-low temperatures (ULT), ranging from 100°C to 350°C.[3] We show that the lowered surface kinetics leads to a pronounced layer supersaturation, allowing us to access layer thicknesses that are more than an order of magnitude larger than previously reported values. We highlight that pristine growth pressures deep in the ultra-high vacuum range ( ≤10-10 mbar) are crucial to keep the density of unwanted impurities in the (Si)Ge layers to a minimum and, thus, enable excellent electrical and optical properties of the grown heterostructures. These low growth pressures are particularly important in ULT growth since the low thermal budget impedes the efficient desorption of residual gas molecules from the substrate.We show that such fully strained, defect-free (Si)Ge epilayers grown directly on SOI substrates form high-quality nanosheets [4] for which properties like thickness, SiGe(Sn) content, and barrier material, doping can be conveniently tuned during the epitaxy process beyond past limitations. These nanosheets are the highly scalable base for advanced transport devices, such as reconfigurable transistors with excellent performance characteristics [4,5,6].

Tuning the Optical and Electrical Properties of ALD-Grown ZnO Films by Germanium Doping.

In this work, we report on the fabrication of ZnO thin films doped with Ge via the ALD method. With an optimized amount of Ge doping, there was an improvement in the conductivity of the films owing to an increase in the carrier concentration. The optical properties of the films doped with Ge show improved transmittance and reduced reflectance, making them more attractive for opto-electronic applications. The band gap of the films exhibits a blue shift with Ge doping due to the Burstein-Moss effect. The variations in the band gap and the work function of ZnO depend strongly on the carrier density of the films. From the surface studies carried out using XPS, we could confirm that Ge replaces some of the Zn in the wurtzite structure. In the films containing Ge, the concentration of oxygen vacancies is also high, which is somehow related to the poor electrical properties of the films at higher Ge concentrations.

Obtaining ultra-high hardness in spark plasma sintered Ge40As40Se20 bulk glass

In order to overcome the narrow glass-forming compositional range with traditional melt-quenching method, we here performed the mechanical milling and Spark Plasma Sintering technology to fabricate a high Ge content chalcogenide glass, the Ge40As40Se20 glass, which locates edge of the Ge-As-Se glass-forming domain. By using the optimal ball milling time of 50 h and sintering stress of 37.5 MPa, the large size Ge40As40Se20 bulk glasses were obtained, which possesses both a large Vickers hardness of 369 kgf/mm2 and a relative high infrared optical transmission of 43 % (@5 and 9 μm). Moreover, it was found there are pores in the sintered glasses more or less, and the pore size and number significantly affect the transmission, i.e., the optimal Ge40As40Se20 bulk glasses were demonstrated has the smallest and least pores via scanning electron microscope. The combination of mechanical milling and low-temperature sintering methods has been confirmed can be used to improve the glass formability and then obtain the high Ge content component with a potential high hardness glass to break through the limited mechanical property of chalcogenides.

Fabrication of (Ge0.42Sn0.58)S Thin Films via Co-Evaporation and Their Solar Cell Applications.

In this study, as a novel approach to thin-film solar cells based on tin sulfide, an environmentally friendly material, we attempted to fabricate (Ge, Sn)S thin films for application in multi-junction solar cells. A (Ge0.42 Sn0.58)S thin film was prepared via co-evaporation. The (Ge0.42 Sn0.58)S thin film formed a (Ge, Sn)S solid solution, as confirmed by X-ray diffraction (XRD) and Raman spectroscopy analyses. The open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and power conversion efficiency (PCE) of (Ge0.42 Sn0.58)S thin-film solar cells were 0.29 V, 6.92 mA/cm2, 0.34, and 0.67%, respectively; moreover, the device showed a band gap of 1.42-1.52 eV. We showed that solar cells can be realized even in a composition range with a relatively higher Ge concentration than the (Ge, Sn)S solar cells reported to date. This result enhances the feasibility of multi-junction SnS-system thin-film solar cells.

Thin and locally dislocation-free SiGe virtual substrate fabrication by lateral selective growth

Locally dislocation-free SiGe-on-insulator (SGOI) is fabricated by CVD. Lateral selective SiGe growth of ∼30%, ∼45% and ∼55% of Ge content is performed around ∼1 μm square Si(001) pillar located under the center of a 6.3 μm square SiO2 on Si-on-insulator substrate which is formed by H2-HCl vapor-phase etching. In the deposited SiGe layer, tensile strain is observed by top-view. The degree of strain is slightly increased at the corner of the SiGe. The tensile strain is caused by the partial compressive strain of SiGe in lateral direction and thermal expansion difference between Si and SiGe. Slightly higher Ge incorporation is observed in higher tensile strain region. At the peaks formed between the facets of growth front, Ge incorporation is reduced. These phenomena are pronounced for SiGe with higher Ge contents. Locally dislocation-free SGOI, which is beneficial for emerging device integration, is formed along 〈010〉 from the Si pillar by lateral aspect-ratio-trapping.

Expansion of chromatic color range and improvement of mechanical properties on Cu–Ge supersaturated solid solution alloys

The Cu–Ge solid solution alloys have a limited color range and relatively low strength due to its limitation of Ge solubility for a solid solution α-Cu phase at room temperature. To extend chromatic color range and to improve mechanical properties of Cu–Ge solid solution alloys, the Cu–Ge alloys with relatively higher Ge content than solubility limit on equilibrium state were fabricated by induction casting. The as-cast Cu–Ge alloys with 7–10 at.%Ge exhibited dual-phase structure composed of α-Cu and ζ-Cu17Ge3 phases with dendritic structure. By annealing at 700 °C for various times and followed quenching processing, the alloys successfully transformed into the supersaturated α-Cu single-phase structure. To confirm the color difference between the supersaturated single α-phase alloys with a high Ge content and the as-cast single α-phase alloys with low Ge content, the reflectivity analysis, CIE L*a*b* color space system, and color difference indicator were used. As a result, it was confirmed that there was a distinct color difference between supersaturated single α-phase alloys and as-cast single α-phase alloys, and the reflectivity and color difference of the alloys significantly depended on Ge content. Moreover, the Vickers hardness of as-cast and solution treated single α-phase alloys highly improved with an increase of Ge content. The influence of Ge content on phase formation, chromaticity and mechanical properties of solid solution Cu–Ge alloys was systematically discussed.