High-density Wiring Research Articles

Electrochemical Corrosion Properties of Commercial Ultra-Thin Copper Foils

Ultra-thin electrodeposited Cu foils have been developed for substrate thinning for mobile devices. Considering the corrosion by residual etchants from the lithography process for high-density circuit wiring, this study investigates the microstructural features of ultra-thin electrodeposited Cu foils with a thickness of 3 μm and their electrochemical corrosion performance in CuCl2-based etching solution. X-ray diffraction and electron backscatter diffraction analyses verify that ultra-thin Cu foils exhibit a random texture and equi-axed grains. Polarization curves show that ultra-thin foils exhibit a higher corrosion potential and a lower corrosion current density compared with conventional (220)-oriented foils with fan-like distributed fine-elongated columnar grains. Chronoamperometric results also suggest that ultra-thin foils possess superior corrosion resistance. The passive layer, mainly composed of CuCl and Cu2O, forms and dissolves in sequence during polarization.

The full stereo drift chamber for the MEG II experiment

The MEG experiment, at the Paul Scherrer Institute (PSI) near Zurich in Switzerland, aims at searching for the charged-lepton-flavor-violating decay μ+arrow e+γ, prohibited in the Standard Model but allowed, at a measurable level, in many of its extensions. MEG has already determined the world best upper limit on the branching ratio: BR(μ+arrow e+γ)<4.2×10−13 at 90% CL with the full data set collected in the years 2009–2013. A further improvement of the MEG single event sensitivity requires a substantial upgrade of the detector performances and, in particular, the complete replacement of the positron tracker. The MEG upgrade experiment (MEG II) is currently under construction and it is conceived in order to further improve the sensitivity by one order of magnitude in three years of data taking. The new positron tracker is a high transparency single volume, full stereo cylindrical Drift Chamber, immersed in a non uniform longitudinal B-field, co-axial to the muon beam line. Due to the high wire density (12 wires/cm2), the use of the traditional feed-through technique as wire anchoring system could hardly be implemented and therefore it was necessary to develop new wiring strategies. The number of wires and the stringent requirements on the precision of their position and on the uniformity of the wire mechanical tension impose the use of an automatic system to operate the wiring procedures. The drift chamber is currently under construction at INFN Lecce and Pisa, and should be completed by the summer 2017 to be then delivered to PSI for commissioning. The upgraded detector, the new drift chamber and its construction technique, will be described.

Effect of Layer Spacing and Line Width of PCB Coil on Resonant Frequency

With the development of electronic science and technology, people have entered the information society, a variety of portable electronic products enter people’s lives. A large number of miniature human implantable medical devices applied to clinical fields. The traditional human implantable medical device power supply is implanted battery, its biggest drawback is the treatment problem after the battery power consumption. Whether it is taken to replace the new battery, or deep into the body, there is a huge risk. Therefore, the portable external wireless charging, it becomes the best choice for human implantable medical devices. Because some of the implanted device volume is very small, they can't accommodate bulky solenoid coil, which seriously restrict the application of wireless charging technology in implantable medical devices. Printed circuit board (PCB) coil has the advantages of high wiring density, small volume, light weight, beneficial to the miniaturization of electronic equipment, they can replace traditional solenoid coil, and applied to the wireless charging technology. In this paper, HFSS software is used to simulate, a large number of simulation experiments are carried out on the PCB with 2 layers coils. At the same time, the electrical parameters such as layer spacing, line width and resonant frequency are analyzed. Finally, the conclusion is: in the case of fixed layer spacing, with the increasing of the line width, the resonance frequency is gradually reduced; but the resonance frequency is reduced to a certain extent, it is not changed. When line width is fixed, with the growing layer spacing, the resonance frequency value is constantly increasing, the resonant frequency of the growth is also more and more slow.

Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates &amp;gt; 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Negative electron affinity GaAs wire-array photocathodes.

Negative electron affinity GaAs wire-array photocathodes have been fabricated by reactive ion etching and inductively coupled plasma etching of bulk GaAs material followed by Cs-O activation. Scanning electron microscope has revealed that the thus obtained high-density GaAs wire arrays had high periodicity, large height, and good morphology. Photoluminescence spectra indicated the wire arrays were of good crystalline quality and free from any obvious damage. Compared to the original GaAs wafer, the photoluminescence peak positions of the wire arrays were somewhat red-shifted, which may be attributed to the temperature effect and strain relaxation. The wire-array structures showed significantly reduced light reflection compared with the original wafer due to the excellent light-trapping effect. Cs-O activation experiments of the GaAs wire arrays have been performed to reveal the effect of incident angle on quantum efficiency. The results show that maximum quantum efficiency was obtained at about 30°. Given these unique electrical and optical properties, a GaAs wire-array photocathode is an attractive alternative to its planar-structured counterpart.

Evaluating conducting network based transparent electrodes from geometrical considerations

Conducting nanowire networks have been developed as viable alternative to existing indium tin oxide based transparent electrode (TE). The nature of electrical conduction and process optimization for electrodes have gained much from the theoretical models based on percolation transport using Monte Carlo approach and applying Kirchhoff's law on individual junctions and loops. While most of the literature work pertaining to theoretical analysis is focussed on networks obtained from conducting rods (mostly considering only junction resistance), hardly any attention has been paid to those made using template based methods, wherein the structure of network is neither similar to network obtained from conducting rods nor similar to well periodic geometry. Here, we have attempted an analytical treatment based on geometrical arguments and applied image analysis on practical networks to gain deeper insight into conducting networked structure particularly in relation to sheet resistance and transmittance. Many literature examples reporting networks with straight or curvilinear wires with distributions in wire width and length have been analysed by treating the networks as two dimensional graphs and evaluating the sheet resistance based on wire density and wire width. The sheet resistance values from our analysis compare well with the experimental values. Our analysis on various examples has revealed that low sheet resistance is achieved with high wire density and compactness with straight rather than curvilinear wires and with narrower wire width distribution. Similarly, higher transmittance for given sheet resistance is possible with narrower wire width but of higher thickness, minimal curvilinearity, and maximum connectivity. For the purpose of evaluating active fraction of the network, the algorithm was made to distinguish and quantify current carrying backbone regions as against regions containing only dangling or isolated wires. The treatment can be helpful in predicting the properties of a network simply from image analysis and will be helpful in improvisation and comparison of various TEs and better understanding of electrical percolation.

Research on Identification of Dust Particles on COF

Chip On Film(COF) is the key component of electronic products, and is different from Printed Circuit Board(PCB). The properties of high flexibility, thin thickness, lightweight and high wiring density make it difficult to inspect COF, especially dust particles interference. Dust particles are similar to defects, and it is hard to identify dust particles from defects, so dust particles interference of quality test is the difficulty of automatic surface defect detection. In this paper, a new method to identify dust particles is discussed from abnormal area called junction points detection and machine learning method Support Vector Machine(SVM) according to the characteristics of dust particles. As a result, a 94.8% correct rate of dust particles images identification has been achieved with the method.

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

High Density Interposer – Challenges and Opportunities

Within “More than Moore” concepts interposer based packaging technologies, known as 2.5D/3D wafer level system integration, open up a wide range of miniaturized multi-functional system solutions. Pending of the final application dedicated interposer concepts have been developed for grabbing multiple active components, fabricated by different suppliers, using different technologies and materials, e.g. sensors, logic, radio frequency (RF) and memory-ICs, as well as passive devices, including antennas. In many cases the application of high density wiring, micro pillar (μ-pillar) interconnects as well as through silicon vias (TSVs) are required. Finally the interposer needs to provide the mechanical basement for system packages. In order to support system miniaturization and extension of system performance on one hand and to meet costs and time to market challenges on the other hand the development of modular interposer concepts as well as the application of dedicated basic interposer technologies is of high interest for R&amp;D, prototyping and small volume applications. A short outline of high density interposer technologies developed and available at Fraunhofer IZM on 300mm substrates will be presented. Starting with a brief discussion of basic elements of interposers, several technology concepts developed and validated for high density interposer applications will be described. Challenges related to μ-pillar applications and high density wiring will be addressed and generic results will be presented. A high level comparison of challenges and opportunities will be shown and discussed. A brief outlook of future development work for system applications will be given.

Advances in Fine Pitch Off-Chip Interconnections Through the Use of a Novel Surface Finish

One constant in electronic system integration is the continuous trend towards smaller devices with increased functionality, driven by emerging mobile and high-performance applications. This brings the need for higher bandwidth at lower power, translating into increased I/O density, to enable highly-integrated systems with form factor reduction. These requirements result in the necessity of interconnection pitch-scaling, below 30 μm in the near future, and substrates with high wiring densities, leading to routing with sub 5 μm L/S where standard surface finishes (ENIG, ENEPIG) are no longer applicable. Copper pillar with solder caps technology is currently the prevalent solution for off-chip interconnections at fine pitch, dominating the high performance and mobile market with pitches as low as 40 μm in production. However, this technology faces many fundamental limitations in pitch scaling below 30 μm, due to solder bridging, IMC-solder interfacial stress management, and poor power handling capability of solders. All-copper interconnections without solder are very sought after by the semiconductor industry and have been applied to 3D-IC stacking, however no cost effective, manufacturable and scalable solution has been proposed to date for HVM and application to non CTE matched package structures. The low temperature Cu-Cu interconnection technology without solder recently patented by Georgia Tech PRC is one of the most promising solutions to this problem. The main bottleneck of copper oxidation is dealt with by application of ENIG on the Cu bumps and pads, enabling formation of a reliable metallurgical bond by thermocompression bonding (TCB) at temperatures below 200°C, in air, with cycle-times compatible with HVM targets. However, to ensure a bump collapse of 3 μm to overcome non-coplanarities and warpage, a pressure of 300MPa is used in the Process-of-Record (PoR) conditions, limiting the scalability of this technology. This paper introduces a novel Electroless Palladium / Autocatalytic Gold (EPAG) surface finish process, to enable the next generation of high density substrates and interconnections. With circa 100nm-thin Pd and Au layers, the EPAG finish can be applied to fine L/S wiring, with no risk of bridging adjacent Cu traces, even with spacing below 5 μm. Further, the EPAG finish is compatible with current interconnection processes; such as wire bonding, and the Cu pillar and solder cap technology for fine-pitch applications. For further pitch reduction, the EPAG surface finish was coupled to GT PRC's low-temperature Cu-interconnections, in an effort to reduce the bonding load for enhanced manufacturability without degrading the metallurgical bond or reliability. This paper is the first demonstration of such interconnections. The effect of the surface finish thickness and composition on the bonding load, assembly yield, quality of the metallurgical bond was extensively evaluated based on analysis of the metal interface microstructures and the chemical composition of the joints. The current PoR using Electroless Nickel / Immersion Gold (ENIG) coated Cu pillars and pads was used as reference. A novel surface finish is introduced, which allows formation of Cu-Cu interconnections without solder at lower pressure, between a silicon die and glass, organic or silicon substrate at fine pitch, allowing the performance improvements demanded by the IC Packaging Industry.

Axial backlighting of two-wire Z-pinch using an X-pinch as an X-ray source

The axial backlighting of two-wire Z-pinch using an X-pinch as an X-ray source was conducted on PPG-1, a pulsed power generator with a current of 400 kA in amplitude and 100 ns in pulse width. Its time-resolved axial backlighting images are obtained. In the backlighting images all the physical processes similar to those occurring in the early stage of the wire-array Z-pinch are observed, including the expansion of the high-density wire core surrounded by low-density coronal plasmas, the motion of the coronal plasma toward the axis of the wire-array, and the formation of precursor plasma. The areal mass density of the plasma shown in the backlighting images is calibrated with step-wedge filters. And the time-resolved radial distributions of the areal mass density of the plasma from the two-wire Z-pinch are obtained.

3D Wafer Level Heterogeneous Integration

3D integration is worldwide considered as one of the most important key technology for microelectronics to meet the growing demands regarding more functionality with concurrent increase in performance as well as miniaturization and cost reduction. So 3D integration is of main relevance for application areas e.g. cyber physical systems, internet of things, ambient assisted living (AAL) as well as information & communication, logistics, security, automotive, health care and industrial electronics. Besides following “More Moore”, Europe is pursuing a strategy on heterogeneous integration approaches following “More than Moore”. In this context, individual and different 3D integration approaches are adapted to the specific application scenarios.Interposers with Through Silicon Vias (TSV) are becoming a very important element for the realization of 3D System in Packages (SiPs). Main advantages of silicon interposers are the decoupling of front end/back end processing for the implementation of TSVs, redistribution layers (RDL) and the integration of active and passive devices. Besides independent manufacturing, interposers can be realized in short time-to-market time frame and in a cost effective way. TSV interposers are designed and manufactured for the different application areas which results also in different technical specifications ranging from high density TSV integration and high density RDL for digital applications to interposers for RF application as well as MEMS integration and optical interconnects.The presentation will highlight results and technical achievements for 3D integration using TSV interposer and addresses as well the broad spectrum of topics from design, technology and reliability related to 3D systems.Concerning technical features, interposers deal with high density wiring redistribution layers (RDL), TSVs and top/bottom side interconnect formation (bumping). This allows the electrical signal routing across the top side and to the interposer back side. Some new applications appear to require up to 4 layers RDL of less than 1μm line/space and silicon oxide/nitride dielectric layer.Silicon interposers with TSVs provide additional features to address 3D-SiP for heterogeneous integration. These include:Device carrier for stacked devices,High density wiring between (stacked) components,3D device stacking using TSVs,Integrated passive devicesEmbedding of active devices into the IP,Functional layer integration (actors, sensors, antennas),Modularization,Integrated test features For the assembly and 3D stack formation of the devices, different interconnection technologies, e.g. micro solder bumps (SnAg) and copper pillars, are used to deal especially with surface topography of the devices and warpage of the board/substrate.Beside silicon interposer, also glass interposers are emerging elements for specific applications. Compared to silicon interposers, glass interposer currently have only limited via dimension and cannot deal with high density TSVs, e.g. <5µm diameter and 10µm pitch. For this, the supply chain is still emerging. The metallization process for silicon interposers is commonly established in wafer fabs. However, most of these facilities do not possess via-last or bumping capability. SUMMARY 3D integration technology is one of the main drivers in packaging and system integration to meet the requirements for high functionality, highly miniaturized smart systems.Future advanced 3D systems will result in complex 3D stacking approaches using the TSV technology. Silicon interposers with TSVs are an important element to combine different advanced devices into one miniaturized system (SiP) with high functionality and to overcome currently existing issues regarding TSV integration into active devices. One important task is the supply chain between e.g. IDMs, OSAT or packing houses.Another crucial aspect is the balance between performance improvement and 3D manufacturing cost (TSV & packaging). So the implementation of 3D integration using TSV and interposer is very product specific. 3D integration requires, beside the technology approaches, also an overall SiP process integration approach which addresses design, technology and reliability.Fraunhofer IZM’s center “All Silicon System Integration Dresden - ASSID” and the Fraunhofer Cluster 3D Integration (http://www.3d-integration.fraunhofer.de/en.html) are focusing on the development and prototyping of 3D systems using Cu-TSVs in active devices (via middle, via last) and silicon interposers as well.

Design of Green Cabling System

The idea of green cabling system includes energy saving and environmental protection. Green cabling system design and installation for energy conservation to reduce energy consumption is significant, and this is also the need for future cabling system an important factor in thinking and direction. Rational design and display cabinet to avoid hot and cold air short circuit. Route planning and reasonable layout, high-density pre-connected wiring products, can significantly reduce the wiring space. So that we can increase the cooling effect of air conditioning and reduce the electricity consumption. Meanwhile, green cabling system should choose Environmental protection cabling products. Driven by three factors (the standards, user needs and technological progress), the concept of Green Cabling technology evolved into the cabling industry trends. With related international, national standards and technology development, Green cabling system design is the focus of this paper.

Sensory and cognitive neurophysiology in rats, Part 1: Controlled tactile stimulation and micro-ECoG recordings in freely moving animals.

We have developed a setup for rats that allows for controlled sensory input to an animal engaged in a task while recording both electrophysiological signals and behavioral output. We record electrophysiological signals using a novel high-density micro-electrocorticography (micro-ECoG) grid that covers almost the whole somatosensory system. We dealt with the well-known difficulty that the rat uses its whisker system in an active (motor-controlled) way to explore its environment by designing a head-mounted device that stimulates the rat's snout in a way unaffected by whisker movements. We replicate the spatial specificity of early evoked responses in somatosensory and auditory cortex. In a companion paper (Cognitive Neurophysiology in Rats, Part 2: Validation and Demonstration) we validate our setup and show for the first time that the ECoG can be used to record evoked responses in a signal that reflects neural output (spiking activity). Compared with high-density wire recordings, micro-ECoG offers a much more stable signal without readjustments, and a much better scalability. Compared with head-fixed preparations, our head-mounted stimulator allows to stay closer to the rat's natural way of collecting sensory information. For perceptual and cognitive research, our setup provides a unique combination of possibilities that cannot be achieved in other setups for rodents.

Sensory and cognitive neurophysiology in rats. Part 2: Validation and demonstration.

We have developed a novel setup for rats that allows for controlled sensory input to an animal engaged in a task while recording both electrophysiological signals and behavioral output. Our setup is described in a companion paper. We validate our setup by replicating (1) the functionally nonspecific spread of neural activity following tactile stimulation, and (2) the effects of anesthesia on the tactile evoked responses. We also demonstrate for the first time that the ECoG can be used to record evoked responses in a signal that reflects neural output (spiking activity), and illustrate the usefulness of our setup by demonstrating that these evoked responses are modulated by both the phase of pre-stimulus oscillations and by expectation. Compared with high-density wire recordings, micro-ECoG offers a much more stable signal without readjustments, and a much better scalability. Compared with extracranial and regular ECoG recordings, micro-ECoG allows us to measure signals that reflect both neural input and neural output. For sensory and cognitive research, our setup provides a unique combination of possibilities that cannot be achieved in other setups for rodents.

Effects of Creep Parameters of Lead-Free Solders on Fatigue Reliability of 3D IC Packages with through Silicon Vias

3D IC packaging technologies are emerging as they are able to respond to the demands for smaller form-factor, faster, high density interconnection at cheaper cost. Moreover, for a 3D IC package, through silicon vias (TSVs) provide high wiring density interconnection, thus improve electrical performance due to shorter interconnection from the chip to the substrate. However, TSV technology is still facing severe challenges as the physical design problems due to the existence of the copper vias remain resolved. Apart from thermal expansion mismatch, the problems are due in part to the nonlinear behavior of SAC lead-free solder used in the package as an echo of environmental concerns and RoHS directive. However, there exists a wide range of values of the parameters of the creep model used to describe the nonlinear behavior of SAC. The effects of the variations of these parameters on the thermal reliability of IC packages, particularly the 3D IC package with built-in TSVs considered herein, is of interest. Presented in the paper is a study on assessment of the influence of the creep parameters of SAC solders on the isothermal fatigue reliability of a 3D IC package with built-in TSVs. The results show that as the strain rate is linear proportional to C1, a larger C1 tends to enlarge the strain rate hence decrease the fatigue life. However, the relationship between the fatigue life of the specific IC package is not linear. Although the variation of C2 causes a large variation in the fatigue life, its effect becomes insignificant when a moderate value of C2 is considered. As a power parameter to the hyperbolic sine function of the creep model, C3 contributes a 40% variation to the fatigue life. Lastly, the fatigue life increases with C4 value, and the gain of fatigue life increases as C4 approaches the upper limit considered herein.

Design and Fabrication of a Silicon Interposer With TSVs in Cavities for Three-Dimensional IC Packaging

Flip chip is one of the packaging techniques for high-performance components. There is a greater demand on integrating more functions in a smaller chip nowadays. This leads to the increase of I/O density. Organic substrate is the bottleneck of the high-density packaging. A silicon interposer with through-silicon vias (TSVs) is commonly used to provide a platform with a high wiring density to redistribute I/Os. After I/O redistribution, larger solder joints with a larger pitch can be used to connect the interposer to the organic substrate. In this paper, a TSV-based silicon interposer with a cavity and copper pillars for 3-D packaging is presented. The cavity hosts the flip-chip device. There are copper-filled TSVs in the cavity to provide the electrical interconnections to the backside of the interposer. Flip-chip solder bumps are electroplated on the copper pillars. Subsequent to the flip-chip assembly process, the device is seated in the cavity entirely. The backside of the flip chip is lower than that of the surface of the interposer. This provides a better environment for further die stacking on the surface of the interposer. The microfabrication process of the proposed silicon interposer with TSVs in cavities is discussed in detail.

Diode probes for spatiotemporal optical control of multiple neurons in freely moving animals.

Neuronal control with high temporal precision is possible with optogenetics, yet currently available methods do not enable to control independently multiple locations in the brains of freely moving animals. Here, we describe a diode-probe system that allows real-time and location-specific control of neuronal activity at multiple sites. Manipulation of neuronal activity in arbitrary spatiotemporal patterns is achieved by means of an optoelectronic array, manufactured by attaching multiple diode-fiber assemblies to high-density silicon probes or wire tetrodes and implanted into the brains of animals that are expressing light-responsive opsins. Each diode can be controlled separately, allowing localized light stimulation of neuronal activators and silencers in any temporal configuration and concurrent recording of the stimulated neurons. Because the only connections to the animals are via a highly flexible wire cable, unimpeded behavior is allowed for circuit monitoring and multisite perturbations in the intact brain. The capacity of the system to generate unique neural activity patterns facilitates multisite manipulation of neural circuits in a closed-loop manner and opens the door to addressing novel questions.

Phase-dependent electron transport through a quantum wire on a surface

Electron transport through a quantum wire in the presence of external periodic energy-level modulations with different on-site phases is studied within the time evolution operator method for a tight-binding Hamiltonian. It is found that in the presence of spatial symmetry of the system and no source–drain and static gate voltages the pumping current can be generated. Moreover, for a wire which is tunnel-coupled to the underlying substrate, the current flowing through an unbiased wire does not fade away but increases with the wire–surface coupling. For randomly chosen phases at every wire site two regimes of the phase-averaged current are found which are related to small and high wire density of states.

Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator Incorporating High Density TSVs and Interconnects

Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers are also promising in terms of high reliability interconnections for large chips due to minimized CTE mismatch compared to standard organic substrates. A silicon interposer including high density TSVs has been successfully processed and fully tested. Process integration has been characterized, electrical results have been analyzed and they will be discussed in this paper. The first half of this paper will focus on integration including several technical challenges such as: 10:1 Aspect Ratio dense TSV of 10μm diameter, damascene metal layers 100,000 25μm diameter micro-bumps per die, and a specific backside redistribution layer, and the electrical data from DC tests achieved after full realization of the silicon interposer. These results show very high yield and a good uniformity among wafers. The later half of this paper will focus on assembly process and reliability test. Conventional mass reflow was performed for each level assembly. As assembly was successfully processed, reliability test which were TC 1000 cycles to check electrical connection on daisy chain and C4 bump, HTS for 1000 hours to observe resistance change on C4 bump and HAST 1000hours to check underfill delamination was performed. All samples passed each reliability test. The results in detail will be discussed in this paper.