Full Integration and Electrical Characterization of 3D Silicon Interposer Demonstrator Incorporating High Density TSVs and Interconnects

Abstract

Silicon interposers with TSVs appear to open new possibilities thanks to high wiring density interconnections and improved electrical performances given by shorter interconnections from die to die and also from die to substrate. Silicon interposers are also promising in terms of high reliability interconnections for large chips due to minimized CTE mismatch compared to standard organic substrates. A silicon interposer including high density TSVs has been successfully processed and fully tested. Process integration has been characterized, electrical results have been analyzed and they will be discussed in this paper. The first half of this paper will focus on integration including several technical challenges such as: 10:1 Aspect Ratio dense TSV of 10μm diameter, damascene metal layers 100,000 25μm diameter micro-bumps per die, and a specific backside redistribution layer, and the electrical data from DC tests achieved after full realization of the silicon interposer. These results show very high yield and a good uniformity among wafers. The later half of this paper will focus on assembly process and reliability test. Conventional mass reflow was performed for each level assembly. As assembly was successfully processed, reliability test which were TC 1000 cycles to check electrical connection on daisy chain and C4 bump, HTS for 1000 hours to observe resistance change on C4 bump and HAST 1000hours to check underfill delamination was performed. All samples passed each reliability test. The results in detail will be discussed in this paper.