High Thermal Budget Research Articles

Annealing of Silicon Heterojunction Solar Cells: Interplay of Solar Cell and Indium Tin Oxide Properties

In this paper, we report the evolution of silicon heterojunction solar cell properties focusing, in particular, on the indium tin oxide (ITO) layers upon consecutive thermal annealing. We find that the charge carrier density N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> of the ITO increases with higher thermal budget, while the carrier mobility remains constant. For the solar cells, their series resistance at the maximum power point R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MPP</sup> first decreases due to the reduction of the ITO's sheet resistance. With further annealing, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MPP</sup> increases again. As all monitored R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> components decrease, we attribute this to an increase of the contact resistance. The implied V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OC</sub> and the implied fill factor both slightly degrade for annealing temperatures above 190 °C for our layers. This, as well as the change in Ne of the ITO, must be carefully considered when optimizing the thermal budget needed, e.g., for sputter damage or screen-printing paste curing.

Approach to suppress the ambipolar current conduction and improve radiofrequency performance in polarity control electrically doped hetero TFET

In this work, a distinctive approach for the suppression of ambipolar behaviour of novel polarity control electrically doped hetero tunnel field effect transistor (TFET) has been reported. For this purpose, a wider band gap material, gallium arsenide phosphide has been employed at drain/channel regions. However, narrow band-gap material, silicon has been used in the source region. This combination of materials leads to a huge reduction in the ambipolar current and significant improvement in ON-state current due to the reduction in the electric field at the drain/channel interface and improvement in tunnelling rate at the source/channel interface, respectively. The proposed device also reduces the drain to source capacitance due to the presence of potential barrier width which leads to improvement in the radiofrequency performance. Therefore, the proposed device is very useful for ultralow power circuit applications. Moreover, polarity gates (PG1 and PG2) have been considered for the formation of n+ (drain) and p+ (source) regions. Hence, the proposed structure avoids ion implantation, random doping fluctuation, and high thermal budget unlike in the case of conventional TFETs, as the latter is physically doped. All the simulations have been performed using ATLAS software.

Thermal Atomic Layer Deposition of Device-Quality SiO2 Thin Films under 100 °C Using an Aminodisilane Precursor

SiO2 is one of the most important dielectric materials that is widely used in the microelectronics industry, but its growth or deposition requires high thermal budgets. Herein, we report a low-temp...

Growth and Characterization of Undoped Polysilicon Thick Layers: Revisiting an Old System

Thick layer of polycrystalline silicon (poly-Si) grown by Atmospheric Pressure Chemical Vapor Deposition (APCVD) is still a reference material in a number of applications, despite the high thermal budget of this technique. This work presents a material study of undoped poly-Si layers of different thicknesses, using different characterization techniques such as secondary electron microscope in backscattered detection configuration, electron backscattering diffraction imaging, secondary ion mass spectrometry and spreading resistance profiling. The poly-Si layers, grown at 1000 °C by APCVD on thermal oxide, were found to have a columnar microstructure with [110] main orientation. By correlating layer purity, grain size and electrical resistivity, no straightforward relation between grain size and resistivity could be found. The layers resistivity is found almost independent on thickness and thus grain size. The possible reasons for such difference with previous other works are discussed taking into account the grain size determination uncertainty and the electrical characterization limitations.

One-dimensional surface wrinkling for twisted nematic liquid crystal display based on ultraviolet nanoimprint lithography

Surface wrinkling method is used to fabricate a 1-dimensional nanostructure. The structure is transferred to an ultraviolet cured polymer which is used as an alignment layer. The anisotropic geometry serves as a guide for aligning liquid crystal molecules uniformly without defects. The TN-LC cell showed a successful LC switching, with a response time of 20.5 ms, and a threshold voltage of 2.00 V. It also exhibited high thermal stability above 180°C. The proposed UV-cured polymers with 1-D nano wrinkle geometry can be a candidate for alternative alignment techniques, for advanced liquid crystal devices with high thermal budgets.

Local Modulation of Electrical Transport in 2D Layered Materials Induced by Electron Beam Irradiation

Effective doping techniques that precisely and locally control the conductivity and carrier polarity, i.e., electron (n-type) or hole (p-type), play a vital role in the remarkable success of Si-based technology and thus are critical for developing useful devices based on two-dimensional layered transition-metal dichalcogenides (TMDs). In contrast to the previous approaches based on either chemical doping or phase transition that requires complex chemicals or a high thermal budget and shows limited tunability and reliability, we propose a simple yet effective electron-beam irradiation (EBI) technique as an alternative for facilitating polarity transformation and transport modulation in selected regions. The EBI process may generate a precise amount of native chalcogen defects in both MoS2 and MoTe2 by controlling the EBI dosage. First-principles simulations support that the presence of native chalcogen vacancies may substantially reduce the band gaps of TMDs. In MoTe2, the progressive evolution of p-type c...

Front and rear contact Si solar cells combining high and low thermal budget Si passivating contacts

In this work we develop a rear emitter silicon solar cell integrating carrier-selective passivating contacts (CSPCs) with different thermal budget in the same device. The solar cell consists of a B-doped poly-Si/SiOx hole collector and an i/n hydrogenated amorphous silicon (a-Si:H) stack acting as electron collector placed on the planar rear and textured front side, respectively. We investigate the passivation properties of both CSPCs on symmetric structures by optimizing the interdependency among annealing temperature, time and environment. The optimized B-doped poly-Si/SiOx reaches a saturation current density of ~10 fA/cm2 on n-type wafers and an implied open circuit voltage (iVOC) of 716 mV. Furthermore, the i/n a-Si:H stack shows an effective carrier lifetime above 4 ms and iVOC of ~705 mV for cell-relevant layers thickness. After a post-deposition annealing in H2, lifetime is above 10 ms and iVOC = 708 mV. Finally, we optimize the optoelectronic properties of indium-based transparent conductive oxide (Indium Tin Oxide ITO and hydrogenated indium oxide IO:H) to reduce parasitic absorption with a gain in short circuit current density of 0.23 mA/cm2. In conclusion, the optimized layer stacks are implemented at device level obtaining a device with VOC = 704 mV, fill factor of 73.8%, a short circuit current of 39.7 mA/cm2 and 21.0% aperture-area conversion efficiency.

Improved performance of Al/n&lt;sup&gt;+&lt;/sup&gt;Ge Ohmic contact andGe n&lt;sup&gt;+&lt;/sup&gt;/p diode by two-step annealing method

Silicon based germanium devices are crucial parts of optoelectronic integration as CMOS feature size continuously decreases. Germanium has attracted increasing attention due to its higher electron and hole mobility, larger optical absorption coefficient as well as lower processing temperature than those of silicon. However, the high diffusion coefficient and low solid solubility about n-type dopant and relatively high thermal budget required for high n-type doping in Ge make it difficult to achieve high activation n-type doping and excellent n&lt;sup&gt;+&lt;/sup&gt;/p shallow junction for source/drain in the nano-scaled n-MOSFET (here MOSFET stands for). The high activation concentration and shallow junction n-type doping in Ge are greatly beneficial to the scaled Ge n-MOSFET technology. In this work, the ohmic contact of Al/n&lt;sup&gt;+&lt;/sup&gt;Ge and Ge n&lt;sup&gt;+&lt;/sup&gt;/p junction fabricated by a combination of low temperature pre-annealing process and excimer laser annealing for phosphorus-implanted germanium are demonstrated. Prior to excimer laser annealing, the samplesare annealed at a relatively low temperature, which can heal the implantation damages preliminarily. Through the optimization of pre-annealing temperature and time, the low temperature pre-annealing step can play a critical role in annihilating the implantation damages and significantly suppressing phosphorus diffusion in the laser annealing process, resulting in a very small dopant diffusion length at a high activation level of phosphorus. Through the combination of ion implantation and two-step annealing technology, the specific contact resistivity (&lt;i&gt;ρ&lt;/i&gt;&lt;sub&gt;C&lt;/sub&gt;) of Al/n&lt;sup&gt;+&lt;/sup&gt;Ge Ohmic contact is measured by CTLM structure. The optimized annealing condition is 400 &lt;sup&gt;o&lt;/sup&gt;C-10 min of low temperature annealing and 150 mJ/cm&lt;sup&gt;2&lt;/sup&gt; of ELA. Under that annealing condition, the ρ&lt;sub&gt;C&lt;/sub&gt; of the sample by two-step annealing is reduced to 2.61 × 10&lt;sup&gt;–6&lt;/sup&gt; Ω·cm&lt;sup&gt;2&lt;/sup&gt;, which is one order of magnitude lower than that by ELA alone (about 3.44 × 10&lt;sup&gt;–4&lt;/sup&gt; Ω·cm&lt;sup&gt;2&lt;/sup&gt;). The lower value of &lt;i&gt;ρ&lt;/i&gt;&lt;sub&gt;C&lt;/sub&gt; for the sample with LTPA can contribute to the higher carrier concentration and better crystalline quality thanthat without LTPA, which is confirmed by SRP and TEM. Moreover, the rectification ratio of Ge n&lt;sup&gt;+&lt;/sup&gt;/p junction diode is improved to 8.35 × 10&lt;sup&gt;6&lt;/sup&gt; at ± 1 V, which is two orders of magnitudes higher than that by ELA alone. And a lower ideality factor of about 1.07 is also obtained than that by ELA alone, which indicates that the implantation damages can be repaired perfectly by two-step annealing method.

(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in Finfet, Stacked Nanowires and Monolithic 3D Integration

Microelectronic devices enable the continuous improvement in mobile data exchange and mobile communication. This exciting technological progress has been achieved by transistor scaling, resulting in an increased performance for lower energy consumption and cost. As CMOS device scaling proceeds, the number of epitaxial growth steps in device fabrication schemes increases. Examples are SiGe or Ge as high mobility channel materials [1-3], SiGe/Si or SiGe/Ge multi-layers to define nanowires in lateral Gate All Around (GAA) devices [3-5], and Source/Drain (S/D) stressor layers which also allow to reduce the S/D contact resistance [3,6-8]. In this contribution we will describe the characteristics of the epitaxial growth schemes as used for Fin and Gate-All-Around (GAA) devices. For Si- and SiGe-channel GAA devices, strained SiGe/Si multi-layers, which are used to define lateral nanowires, can be grown with conventional precursors (SiH4 or SiCl2H2 and GeH4). The compositional gradient is sufficiently steep to allow efficient wire release by selective SiGe or Si removal [2,5,9]. In case of Ge GAA, epitaxial growth of Ge-rich SiGe/Ge on SiGe Strain Relaxed Buffers is more challenging. Extremely low process temperatures are required to avoid strain relaxation. These layers need to be grown with higher order precursors, since conventional precursors become ineffective [4]. The epitaxial growth of ultra-thin Si layers on (strained) Ge fins or lateral nanowires used to passivate Ge surfaces in the high-k gate module has been discussed at the ECS Fall meeting of 2017 [10] and will not be covered in this presentation. A major challenge is to increase the active doping concentration in epitaxial S/D layers. Current scaling of gate and fin pitch reduces contact area and the contact resistance becomes a key contributor to device parasitics [7,11]. In addition, monolithic 3D integration, requires to reduce the thermal budget of the complete epitaxial growth scheme (including pre-epi surface cleaning). For Si:P, we demonstrated that P doping activation can be increased by post-epi anneals (>1e21 cm-3) without major strain loss [8]. Nearly similar active doping concentrations (up to 8e20 cm-3) are obtained by using Si3H8 instead of SiCl2H2 and low growth temperatures without the need for a post epi thermal treatment. For SiGe:B, we obtained similar active boron concentrations using conventional precursors [12,13]. Because of the low boron solubility in Ge, it is more challenging to fabricate S/D Ge pMOS contacts with the right lattice constant (to act as a stressor) and with a sufficiently high active doping concentration. Effort is ongoing to increase the active boron concentration by moving the growth process further away from equilibrium. This is done at low growth temperatures by either using Ge2H6 as high-order precursor or by assessing new materials such as GeSn. On blanket wafers, higher active doping concentrations have been reported but it is extremely challenging to translate this into a selective growth process without Sn precipitation. This triggered the research community to assess alternative dopants. For Ge, the Ga doping solubility is significantly higher than that of B. Epitaxial growth schemes are preferred above ion implantation as the latter one requires an unwanted high thermal budget for doping activation and on patterned wafers it does not allow conformal doping profiles. First Ge:Ga layers with a resistivity below 0.4 mΩ.cm have been grown without any detectable C incorporation. In addition, Ga + B co-doping enables to reduce the resistivity of SiGe:B:Ga, which confirms the potential of Ga as an add-on. Acknowledgements The imec core CMOS program members, European Commission, the TAKEMI5 ECSEL project, local authorities and the imec pilot line are acknowledged for their support. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases.

New Route for "Cold-Passivation" of Defects in Tin-Based Oxides.

Transparent conductive oxides (TCOs) are essential in technologies coupling light and electricity. For Sn-based TCOs, oxygen deficiencies and undercoordinated Sn atoms result in an extended density of states below the conduction band edge. Although shallow states provide free carriers necessary for electrical conductivity, deeper states inside the band gap are detrimental to transparency. In zinc tin oxide (ZTO), the overall optoelectronic properties can be improved by defect passivation via annealing at high temperatures. Yet, the high thermal budget associated with such treatment is incompatible with many applications. Here, we demonstrate an alternative, low-temperature passivation method, which relies on cosputtering Sn-based TCOs with silicon dioxide (SiO2). Using amorphous ZTO and amorphous/polycrystalline tin dioxide (SnO2) as representative cases, we demonstrate through optoelectronic characterization and density functional theory simulations that the SiO2 contribution is twofold. First, oxygen from SiO2 passivates the oxygen deficiencies that form deep defects in SnO2 and ZTO. Second, the ionization energy of the remaining deep defect centers is lowered by the presence of silicon atoms. Remarkably, we find that these ionized states do not contribute to sub-gap absorptance. This simple passivation scheme significantly improves the optical properties without affecting the electrical conductivity, hence overcoming the known transparency–conductivity trade-off in Sn-based TCOs.

Chromium Trioxide Hole-Selective Heterocontacts for Silicon Solar Cells.

A high recombination rate and high thermal budget for aluminum (Al) back surface field are found in the industrial p-type silicon solar cells. Direct metallization on lightly doped p-type silicon, however, exhibits a large Schottky barrier for the holes on the silicon surface because of Fermi-level pinning effect. As a result, low-temperature-deposited, dopant-free chromium trioxide (CrO x, x < 3) with high stability and high performance is first applied in a p-type silicon solar cell as a hole-selective contact at the rear surface. By using 4 nm CrO x between the p-type silicon and Ag, we achieve a reduction of the contact resistivity for the contact of Ag directly on p-type silicon. For further improvement, we utilize a CrO x (2 nm)/Ag (30 nm)/CrO x (2 nm) multilayer film on the contact between Ag and p-type crystalline silicon (c-Si) to achieve a lower contact resistance (40 mΩ·cm2). The low-resistivity Ohmic contact is attributed to the high work function of the uniform CrO x film and the depinning of the Fermi level of the SiO x layer at the silicon interface. Implementing the advanced hole-selective contacts with CrO x/Ag/CrO x on the p-type silicon solar cell results in a power conversion efficiency of 20.3%, which is 0.1% higher than that of the cell utilizing 4 nm CrO x. Compared with the commercialized p-type solar cell, the novel CrO x-based hole-selective transport material opens up a new possibility for c-Si solar cells using high-efficiency, low-temperature, and dopant-free deposition techniques.

Ultra-low-energy ion-beam synthesis of nanometer-separated Si nanoparticles and Ag nanocrystals 2D layers

2D networks of Si and Ag nanocrystals have been fabricated in the same SiO2 matrix by Ultra-Low-Energy Ion-Beam-Synthesis. Our synthesis scheme differs from a simple sequential ion implantation and its key point is the control of the matrix integrity through an appropriate intermediate thermal annealing. Si nanocrystal layer is synthesised first due to high thermal budget required for nucleation, while the second Ag nanocrystal plane is formed during a subsequent implantation due to the high diffusivity of Ag in silica. The aim of this work is to show how it is possible to overcome the limitation related to ion mixing and implantation damage to obtain double layers of Si-NCs and Ag-NCs with controlled characteristics. For this, we take advantage of annealing under slight oxidizing ambient to control the oxidation of Si-NCs and the Si excess in the matrix. The nanocrystal characteristics and in particular their position and size can be adjusted thanks to a compromise between the implantation energy, the implanted dose for both Si and Ag ions and the intermediate annealing conditions (atmosphere, temperature and duration).

LPCVD in-situ doped silicon for thermoelectric applications

In semiconductor industry doping of polysilicon materials is often achieved with ion-implantation, provoking a relatively high thermal budget. In this study we have analyzed an alternative approach via low pressure chemical vapor deposition (LPCVD) in-situ phosphorus doping with subsequent rapid thermal anneal (RTA) on 150mm/300mm wafers in order to obtain Si-based materials for thermoelectric applications. With this process integration a lower thermal budget, a release of film stress and an enhancement of throughput are reached. Additionally, the dopants are distributed uniformly and there are more process tuning possibilities. The investigation includes time-of-flight secondary ion mass spectrometry (ToF-SIMS) for depth profiling of the dopant and X-Ray diffraction (XRD) and scanning electron microscopy (SEM) analysis for microstructure analysis. Film stress was also calculated from wafer bow measurement. The LPCVD amorphous silicon in-situ P-doped (a-Si:P) with RTA and LPCVD polycrystalline silicon in-situ P-doped (poly-Si:P) with RTA thin films were patterned in order to investigate the thermoelectric properties. The results suggest these LPCVD in-situ P-doped Si-based materials as suitable candidates for practical applications in the semiconductor industry.

Improved interface characteristics of Mo/SiO2/4H-SiC metal-oxide-semiconductor with post-metallization annealing

The effects of post-metallization annealing (PMA) have been investigated for thermally-grown SiO2 on 4H-SiC metal-oxide-semiconductor (MOS) with a molybdenum (Mo) gate electrode. Mo is a great metal gate material for Silicon carbide (SiC) due to its high thermal budget and low thermal expansion coefficient, which allows high-temperature processing after the gate electrode formation. In this study, PMA process was carried out after Mo gate formation on thermally-grown SiO2/4H-SiC in the temperature range from 600 to 1000 °C in N2 or a forming gas ambient. The fabricated Mo/SiO2/4H-SiC MOS device annealed at 800 °C exhibited excellent interface characteristics with negligible hysteresis in comparison with as-grown or post-oxidation annealed samples.

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Microstructure and charge trapping in ZrO2- and Si3N4-based superlattice layer systems with Ge nanoparticles

Ge was deposited on silicon as a superlattice with 10 layers of Ge embedded in Si3N4 or ZrO2 matrices via plasma enhanced chemical vapor deposition or RF-sputtering, respectively. Raman spectroscopy, transmission electron microscopy and capacitance-voltage (CV) measurements were performed in order to investigate the structural and electrical properties of the superlattices. It will be shown that, in contrast to furnace annealing, flash lamp annealing of Ge-ZrO2-superlattices leads to crystalline Ge nanoparticles in an amorphous matrix. As revealed by CV measurements, these layers show excellent charge storage capabilities. In comparison, a higher thermal budget is needed to crystallize Ge in case of Si3N4-based superlattices, and no significant charge trapping could be detected during CV measurements.

A Complex Interrelationship between Temperature-Dependent Polyquaterthiophene (PQT) Structural and Electrical Properties

The influence of annealing temperature on the structural and electrical properties of conjugated poly(dodecyl-quaterthiophene) (PQT-12) polymer films is exploited. The temperature induced changes of structural parameters are monitored by in situ grazing incident X-ray diffraction (GIXD) and the conductivity. They are complemented by studies of the dielectric properties using variable angle spectroscopic ellipsometry (VASE). An increase of the scattered intensity, the size of the crystalline domains, and the current response is observed for a first thermal cycle with stepwise heating up to 90 °C, which revealed two polymorphs with different degrees of interdigitation in PQT-12. Irreversible changes are observed for the second cycle with a higher thermal budget up to 140 °C and are connected with a transition from the highly ordered to powder-like disordered phase for the main PQT-12 form whereas the second polymorph with stronger interdigitation completely vanished. In agreement with these observations hig...

Characteristics of silicon oxynitride films grown by using neutral-beams and inductively coupled plasma

The characteristics of silicon oxynitride (SiON) films grown using neutral-beam and typical plasma-enhanced chemical vapor deposition methods are compared. Neutral-beam and plasma oxynitridation processes were performed using a nitrogen neutral beam at room temperature and a nitrogen plasma at 400°C, respectively, using the same deposition system. The neutral beam was generated via the surface neutralization of the ions produced by the inductively coupled plasma. The physical and electrical properties were measured using metal-insulator‑silicon structures. The plasma SiON films showed significant plasma-induced damage, while we demonstrate that the neutral beam method is suitable for growing SiON films at room temperature without plasma-induced damage or a high thermal budget.

Thermal Evolution of Implantation Damages in Mg-Implanted GaN Layers Grown on Si

Localized p-doping is a keystone in the development of many GaN based devices that need selectively doped pocket area such as MOSFETs or PIN diodes. Electrical activation of implanted Mg has been obtained lately with GaN grown on sapphire substrate using an AlN based protective layer combined with multi cycle of rapid thermal annealing at very high temperature (>1300 °C) proving the feasibility and interest of the method [1]. The use of Si (111) substrate allows a better integration of the process on microelectronic production line. However the growth of GaN on Si (111) is less mature and necessitates a buffer usually composed of a complex staking based on AlN intermediate layers [2]. The difference in lattice parameters and thermal extension coefficient in the stacking may make the samples more unstable during the high thermal budget required for doping activation. In the last few years, several groups focused their research on the prevention of GaN surface degradation at high temperature [3] and we have shown that a combination of in situ epi deposited AlN and SiN thin layers is very efficient to avoid this phenomena [4]. Here, we propose to study the impact of high thermal annealing on the evolution of the damage in Mg-implanted GaN (on Si). Indeed, comprehensive studies of the GaN healing mechanism in this kind of structures are not yet reported. We use samples of GaN layer grown by MOCVD on Si (111) using an AlN based buffer layer and protected by an AlN/SiNx cap layer. These samples are implanted with Mg fluences ranging from 1013 to 1015 at/cm² corresponding to maximum effective concentration between 5.1017 and 5.1019 at/cm3 in the implanted layer. 400 °C -1100 °C anneals are proceeded in controlled N2 atmosphere. X-Ray Diffraction (XRD) and Photoluminescence (PL) measurements point out that ion implantation induced damage are healed thanks to different mechanisms: both lattice strain relaxation and point defect annihilation can occur during annealing with different kinetics. Indeed as we can see on Fig.1a, on samples implanted with low to medium fluence (up to 1014 at/cm²), relatively low temperature anneals (< 450 °C) are enough to obtain a near complete correction of the lattice deformation. However, surprisingly, the PL spectra of 400 °C annealed samples shown on Fig1.b indicates that a lot of non-radiative defects are still present and shutting down the PL intensity. The spectra of the sample annealed at 1100°C exhibits bands characteristic of Mg in Ga site (Mg(Ga)) which proves the necessity of a higher thermal treatment to reduce non radiative defects concentration and promote Mg incorporation in the GaN lattice. As shown on Fig 2.a, an increase of the fluence (1015 at/cm²) leads to an increase of the induced strain but also of the temperature necessary to fully relax it (1100°C). However, the PL spectra (Fig 2.b) indicates that even after such a high thermal treatment, the PL intensity of the bands associated with Mg(Ga) is weaker than for medium fluence despite the higher Mg concentration in the matrix [4]. We assume that this behavior may be due to residual damage. This is supported by Transmission Electron Microscopy images of the layer (not shown here) that evidence remaining defective pockets after a 1 h 1100 °C in N2 annealing. These results give insight on the healing mechanism occurring during the activation anneal of Mg implanted in GaN. They also highlight that damage management is a critical parameter for GaN (on Si) p-doping via Mg implantation. To reach this objective, we will show that it is necessary to implement further specific processes to limit the implantation induced damage and to improve the damage recovery efficiency. 1. Tadjer, M.J., et al., Selective p-type Doping of GaN:Si by Mg Ion Implantation and Multicycle Rapid Thermal Annealing. ECS Journal of Solid State Science and Technology, 2015. 5(2): p. P124-P127. 2. Charles, M., et al., The effect of AlN nucleation temperature on inverted pyramid defects in GaN layers grown on 200 mm silicon wafers. Journal of Crystal Growth, 2017. 464: p. 164-167. 3. El-Zammar, G., et al., Surface state of GaN after rapid-thermal-annealing using AlN cap-layer. Applied Surface Science, 2015. 355: p. 1044-1050. 4. Lardeau-Falcy, A., et al., Capping stability of Mg-implanted GaN layers grown on silicon. physica status solidi (a), 2016. Figure 1

New Understanding of Random Telegraph Noise Amplitude in Tunnel FETs

As one of the important sources of lowfrequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of highamplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> ) and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance.