High Temperature Rapid Thermal Annealing Research Articles

Residual-stress relaxation in polysilicon thin films by high-temperature rapid thermal annealing

Rapid thermal annealing reduces stress in a very short time, compared to regular furnace annealing, and can be an effective method for relaxing residual stress in polysilicon thin films. In this work, the effects of regular furnace and high-temperature rapid thermal annealing (RTA) on the residual stress of LPCVD polysilicon thin films have been investigated. The as-deposited 0.5 μm thick polysilicon films have an initial compressive stress of about 340 MPa, and the residual stress is relaxed quickly after a few cycles of RTA at higher temperatures. The stress dependence on annealing time at temperatures of 900–1150 °C has been analysed. Using X-ray diffraction (XRD), micro-Raman spectroscopy and transmission electron microscopy (TEM), we have studied the changes in the microstructure of the thin films induced by the RTA during the stress relaxation. Furthermore, variations in the composition of the surface layer due to annealing have been characterized by X-ray photoelectron spectroscopy (XPS).

Rapid thermal annealing of polysilicon thin films

In comparison with conventional heat treatment, high-temperature rapid thermal annealing (RTA) in a radio frequency (RF) induction-heated system can reduce or eliminate residual stresses in thin films in a few seconds. In this work, changes in the stress level due to the RTA of polycrystalline silicon thin films were studied as a function of annealing time and temperature. The corresponding variations in the microstructure and surface layer of the thin films were experimentally investigated by a variety of analytical tools. The results suggest that the residual stress evolution during annealing is dominated by two mechanisms: 1) microstructure variations of the polysilicon thin film and 2) effects of a surface layer formed during the heat treatment. The fact that the microstructure changes are more pronounced in samples after conventional heat treatment implies that the effects of the formed surface layer may dominate the final state of the residual stress in the thin film.

The Influence of Fluorine on Boron‐Enhanced Diffusion in Silicon by BF2+ Implantation Through Oxide during High Temperature Rapid Thermal Anneal

implantation through a sacrificial oxide for the formation of p+/n shallow junctions is frequently applied in device fabrication. The effects of fluorine on boron diffusion in and out of a silicon substrate during nitrogen‐ambient high temperature rapid thermal annealing have been studied. By comparing B and implanted substrates, it is shown that fluorine out‐diffusion during high temperature annealing coincides with enhanced boron out‐diffusion into the oxide and suppressed boron diffusion into the substrate. In particular, when fluorine accumulated at the end of range dislocation loops is driven out of the bulk, shallower junctions are observed.

Comparison of GaN, InN and AlN powders for susceptor-based rapid annealing of group III nitride materials

We have compared the use of GaN, InN and AlN powders for providing a nitrogen partial pressure within a graphite susceptor during high-temperature rapid thermal annealing of GaN, AlN, InN and InAlN. At temperatures above vapour transport of In from InN powder produces In droplet condensation on the surface of all nitride samples being annealed. GaN powder provides better surface protection than AlN powders for temperatures up to when annealing GaN and AlN samples. Dissociation of nitrides from the surface is found to occur with approximate activation energies of 3.8 eV, 4.4 eV and 3.4 eV, respectively, for GaN, AlN and InN.

Reliable 0.28 μm metal contact technology

A reliable small metal contact (MC) process is developed for the gigabit scaled dynamic random access memories (DRAMs). The high aspect ratio contact etch was accomplished by using a high density inductively coupled plasma reactor. The low contact resistance of the MC for the gigabit scaled DRAMs is realized when the amount of Si consumption at the bottom of the contact holes is minimized (<20 nm). The dopant activation of the source and drain (S/D) regions is also critical to have low contact and sheet resistances (Rc and Rs). Use of the high temperature (>950 °C) rapid thermal annealing enhances the dopant activation and effectively reduces the Rc and Rs. Surface treatment of the bottom of the contact hole after dry etch, becomes a key factor to have low contact resistance in the case of small contacts. The conventional Ar+ in situ sputter cleaning deteriorates the contact resistance of the vertically sloped small MCs. Light etch using CF4 and O2 gases removes damaged layer and improves contact resistance. Rapid thermal nitridation after TiN barrier metal deposition also improves electrical properties of the MCs.

Controlled two-step solid-phase crystallization for high-performance polysilicon TFT's

Solid-phase crystallization for polysilicon thin-film transistors (TFT's) is generally limited by a tradeoff between throughput and device performance. Larger grains require lower crystallization temperatures, and hence, longer crystallization times. In this letter, a novel crystallization technique is presented which increases both throughput and device performance, using a two-step process, controlled using an in situ acoustic temperature/crystallinity sensor. A high-temperature rapid thermal annealing (RTA) nucleation step is followed by a low-temperature grain growth step to grow large-grain polysilicon. TFT's have been fabricated with a substantial improvement in throughput and device performance. This promises a high-throughput, high-performance, spatially uniform TFT process.

Ion implantation in group III-nitride semiconductors: a tool for doping and defect studies

Ion implantation is a flexible process technology for introducing an array of doping or compensating impurities into semiconductors. As the crystal quality of the group III-nitride materials continues to improve, ion implantation is playing an enabling role in exploring new dopant species and device structures. In this paper we review the recent developments in ion implantation processing of these materials with a particular emphasis on how this technology has brought new understanding to this materials system. In particular, the use of ion implantation to characterize impurity luminescence, doping, and compensation in III-nitride materials is reviewed. In addition, we address the nature of implantation induced damage in GaN which demonstrates a very strong resistance to amorphization while at the same time forming damage that is not easily removed by thermal annealing. Finally, we review the coupling of implantation with high temperature rapid thermal annealing to better understand the thermal stability of these materials and the redistribution properties of the common dopant (Si, O, Be, Mg, Ca, and Zn).

The Impacts of Back-End High Temperature Thermal Treatments on the Characteristics and Gate Oxide Reliability of Thin Film Transistor in Ultra Large Scale Integrated Circuit Process

The impacts of the two major high temperature treatments on the characteristics of thin film transistors (TFT's) in the back-end process of ultra large scale integrated circuit (ULSI) technology have been investigated. TFT's without any high temperature treatment show poor characteristics. High temperature furnace annealing and rapid thermal annealing (RTA) which are performed for boron phosphorous tetra ethyl ortho silicate (BPTEOS) planarization can improve the characteristics of low temperature recrystallized TFT. Then, the technologies used for contact annealing result significant difference on the characteristics of TFT's. High temperature furnace contact annealing can still greatly improve the characteristics of TFT's. However, after furnace annealing for BPTEOS planarization, RTA contact annealing deteriorates the characteristics of TFT. High temperature furnace annealing for BPTEOS planarization improves the charge to breakdown (Q bd) value of the gate oxide of TFT and so does the furnace contact annealing. However, RTA contact annealing performed after the furnace planarization flow deteriorates that of the gate oxide.

Spatial variations in oxygen precipitation in silicon after high temperature rapid thermal annealing

Spatial variations of oxygen precipitation have been studied in silicon wafers submitted to rapid thermal annealing (RTA) in nitrogen ambients at a temperature above 1150 °C prior to a two-step precipitation treatment. The samples submitted to high temperature preannealing show a consistent enhancement of oxygen precipitation, which is dependent on the RTA time and temperature. Oxygen precipitate density measurements show that oxygen precipitation is not homogeneous inside the wafer, but peaks near the surfaces, with a minimum in the bulk. The high treatment in N2 results in the formation of defects which act as precursors for the subsequent nucleation and growth of oxygen precipitates. There is strong evidence that these precursors are generated by the thermal nitridation of the silicon surface and subsequent vacancy injection into the bulk of the wafer.

Effects of high temperature rapid thermal annealing using a flat gas flame on the electrical properties of phosphorus-doped polycrystalline silicon films

The effects of high temperature rapid thermal annealing (HT-RTA) using a flat gas flame on the electrical properties of phosphorus-doped polycrystalline silicon (poly-Si) films in association with their microscopic structure were studied. Samples with a phosphorus concentration of 3.1×1017–6.0×1020 cm−3 were prepared and annealed by HT-RTA ranging from 1150 to 1350 °C. During HT-RTA, the sample surface was laterally swept by gas flames. The resistivity of the samples decreased with increasing annealing temperature, and the lowest resistivity was 4.8×10−4 Ω cm for the sample doped with P of 6.0×1020 cm−3 when annealed at 1350 °C. Hall mobility, on the other hand, increased first and then decreased with increasing P concentration. The highest Hall mobility was 71.3 cm2/V s for the sample annealed at 1350 °C of which the P concentration was 3.5×1019 cm−3. The results suggest that the grain boundary potential barriers for carriers decreased with increasing doping concentration and annealing temperature, and that the total area of grain boundaries in the films decreased with increasing annealing temperature because of secondary grain growth and the shrinkage of boundary width.

Ion implantation and rapid thermal processing of Ill-V nitrides

Ion implantation doping and isolation coupled with rapid thermal annealing has played a critical role in the realization of high performance photonic and electronic devices in all mature semiconductor material systems. This is also expected to be the case for the binary III-V nitrides (InN, GaN, and A1N) and their alloys as the epitaxial material quality improves and more advanced device structures are fabricated. In this article, we review the recent developments in implant doping and isolation along with rapid thermal annealing of GaN and the In-containing ternary alloys InGaN and InAlN. In particular, the successful n- and p-type doping of GaN by ion implantation of Si and Mg+P, respectively, and subsequent high temperature rapid thermal anneals in excess of 1000°C is reviewed. In the area of implant isolation, N-implantation has been shown to compensate both n- and p-type GaN, N-, and O-implantation effectively compensates InAlN, and InGaN shows limited compensation with either N- or F-implantation. The effects of rapid thermal annealing on unimplanted material are also presented.

Morphology and photoluminescence improvements from high-temperature rapid thermal annealing of GaN

Rapid thermal annealing of GaN in an Ar or N2 ambient up to 1100 °C is shown to improve surface morphology and photoluminescence intensity. For both ambients the average rms surface roughness as determined by atomic force microscopy decreases from ∼4 nm on the as-grown material to ∼1 nm after a 1100 °C anneal. The band-edge luminescence intensity was increased by a factor of 4 after a 1100 °C anneal in a N2 ambient and a factor of 2 for annealing at 1100 °C in an Ar ambient as compared to as-grown material. The 1100 °C anneal improves the ratio of band edge to deep-level luminescence and also reduces the electron concentration and mobility. The reduction in mobility can be explained in terms of a two-band conduction mechanism where defect band conduction dominates at the lower carrier densities or an increase in the free-carrier compensation ratio.

Impact of high‐temperature rapid thermal annealing in deep‐submicrometer CMOSFET design

AbstractWe investigated the impact of high‐temperature rapid thermal annealing (HT‐RTA) for CMOSFET design in the deep‐submicrometer regime. HT‐RTA (>1000 °C) carried out immediately after ion implantation can reduce the transient enhanced diffusion of implanted impurities and suppress interactions between these impurities, both of which are usually observed in low‐temperature furnace annealing processes. HT‐RTA is definitely effective in CMOSFET design optimization, since it can control impurity profiles more precisely than conventional thermal processes, leading to improvements in the short‐channel effects, current drivability, and reliability of MOSFETs. We also show that HT‐RTA serves as a methodology for analyzing the RSCE (reverse short‐channel effects) and ESCE (enhanced short‐channel effects) taking place simultaneously in deep‐submicrometer MOSFETs.

TiSi2 Phase Transformation by Amorphization Techniques

AbstractULSI packing density calls for sub-micron line widths, but on n-type polysilicon this can lead to incomplete titanium silicide C49 to C54 phase transformation after a conventional two step rapid thermal anneal (RTA). This study compares three different ion beam amorphization techniques: preamorphization, ion beam mixing and silicide amorphization, aiming at a complete phase transformation for submicron silicide lines. For preamorphization, an arsenic implantation at moderate energies (35–75 keV) was used to amorphize the top layer of the polysilicon prior to the titanium deposition. Ion beam mixing used a high-energy (200 keV) arsenic implantation after the titanium deposition to create an amorphous mix of silicon and titanium. These two methods did, each by themselves, lead to an increased fraction of C54 silicide grains already during the low temperature RTA, and a complete phase transformation during the subsequent high temperature RTA. Both methods lowered the thickness difference between titanium silicide on p- and n-type silicon. Silicide amorphization with 75 keV arsenic or 100 keV antimony, applied before the second RTA, did not significantly improve the silicide phase transformation.

Characteristics of in situ deposited GaAs metal-insulator-semiconductor structures

GaAs based metal-insulator-semiconductor structures utilizing a pseudomorphic Si interface layer were investigated. Deposition involved molecular beam epitaxy for GaAs and remote plasma enhanced chemical vapor epitaxy for Si and insulator (Si 3N 4) layers, all without exposure to air. As determined by the conductance method, interface trap densities in the upper 10 10 eV −1 cm −2 were obtained, with samples withstanding high temperature rapid thermal annealing. Frequency dispersion and hysteresis of under 100 mV indicate the quality of the interface and bulk layers. Bulk trap density in the insulator appears to be below 10 12 cm −2. Metal-insulator-semiconductor field-effect-transistors were fabricated and investigated. With GaAs channels, excess channel conduction which vanished at low temperatures was observed. Addition of as low as 5% InAs in the channel eliminated this excess channel current. A similar observation was made when a Ge interface layer was grown on GaAs prior to the Si layer. The excess current is attributed to interfacial traps below the midgap. Transconductances as high as 160 and 170 mS/mm have been obtained with about 2.5 μm gate length in GaAs and InGaAs channels, respectively.

Radical-Beam-Induced Surface Reaction Processes of Porous Si

A new-low temperature dry oxidation process, unlike the presently used methods of wet chemical processing or high-temperature rapid thermal annealing, for the oxidation of porous silicon (PS) is described. In this process the active oxygen radical species from an electron cyclotron resonance plasma were employed for the first time to achieve room-temperature oxidation of PS. This process allows manipulation of the PS surface chemistry which has resulted in both the enhancement and stabilization of the photoluminescence (PL) intensity. These results are explained on the basis of a proposed model in which surface-induced processes incorporate oxygen atoms not only in the outermost Si–O–Si layer but also in the backbonded Si of PS. Furthermore, it is shown that this backbond oxidation is the main mechanism responsible for the enhancement and stabilization of the PL intensity.

Formation of Si–SiO2 stacked-gate structures by plasma-assisted and rapid-thermal processing: Improved device performance through process integration

Formation of Si–SiO2 stacked-gate heterostructures requires (i) preparation of Si surfaces prior to interface formation and oxide deposition, (ii) oxide deposition, (iii) polysilicon gate electrode deposition, and generally (iv) post-deposition doping of the gate electrode. Mid- and/or end-process rapid thermal annealing performed in inert or oxidizing ambients may also be necessary to optimize device performance. Four phases in the development of an integrated processing protocol for stacked-gate structures are described in which these steps have been modified, and continuously improved. Process tools have evolved from (i) single-function chambers for (a) surface cleaning/passivation, and (b) thin film deposition, to (ii) dual-function/single process plasma chambers for (a) in-situ surface cleaning and interface formation and (b) oxide deposition, and finally to (iii) multi-function/dual process chambers in which all of the above process steps are done in situ, but by more than one processing technique. This last approach has culminated in chambers which can accommodate (i) low-temperature plasma-assisted interface formation at ∼300 °C, (ii) intermediate-temperature rapid thermal dielectric and polysilicon depositions at 600–800 °C, and (iii) higher-temperature rapid thermal annealing at 900–1000 °C.

Interface evolution and epitaxial realignment in polycrystal/single crystal Si structures

Our recent work on the poly/single crystal Si interface evolution and on the epitaxial realignment under high temperature (∼ 1000°C) rapid thermal annealing is reviewed. The roles of the mucrystalline morphology, of the interfacial native oxide film, of the doping level and of the processing temperature on the realignment kinetics are addressed. Two different realignment modes are observed. For undoped layers a quasi planar interface motion occurs, while in highly doped polycrystalline layers the realignment proceeds via the formation of epitaxial columns and their lateral growth. These two different modes arise from the doping enhancement of the interface kinetics. It is shown that these processes can be interpreted within an Avrami-Mehl-Johnson nucleation and growth scheme. In the early stages of interface realignment the process is controlled by oxide clustering, arising from the evolution of the native oxide layer, and by the density of grain boundaries intersecting the interface with the single crystal. Once nucleated at specific sites the epitaxial front can then proceed, the kinetics and mode of realignment depending on the density of nucleation sites and on the growth velocity. It is also demonstrated that when narrow (∼ 0.25 μm) polycrystalline strips defined by oxide layers (as in real devices) are used in place of infinite planar layers the realignment mode and kinetics change due to the presence of size effects. These data are presented and their implications for applications to bipolar devices are discussed.

Polycrystalline silicon thin-film transistors with two-step annealing process

Thin-film transistors (TFTs) were fabricated from poly-Si crystallized by a two-step annealing process on glass substrates. The combination of low-temperature furnace annealing and high-temperature rapid thermal annealing leads to a significant improvement in the material quality. The TFTs obtained with this two-step annealing material exhibit better measured characteristics than those obtained by using conventional furnace annealing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High-performance submicrometer undergated thin-film transistors without high-temperature rapid thermal annealing or plasma hydrogenation

High-performance submicrometer undergated thin-film transistors (TFTs) are fabricated without using high-temperature rapid thermal annealing or plasma hydrogenation. These processes are used in the state-of-the-art devices, but avoided in current manufacturing. For a 0.35- mu m*0.35- mu m device and a 0.7- mu m*0.5- mu m device, I/sub ON/ of 3 and 1.2 mu A are obtained with ON/OFF current ratios of 4*10/sup 5/ and 1.2*10/sup 8/, respectively, very close to that of state-of-the-art devices. A new lightly-doped-drain (LDD) structure is employed to improve I/sub ON/ reproducibility, which is difficult to achieve for deep-submicrometer devices with the conventional lightly-doped-offset (LDO) structure. >