High Temperature Rapid Thermal Annealing Research Articles

(Invited) Vertically Stacked Graphene Junction Diodes

Graphene is expected to be nanomaterial of the post-silicon era because of its numerous advantageous properties. The single crystal graphene thermally grown on SiC substrate is considered the most promising platform for future electric devices. Large area epitaxial graphene on SiC substrate has been successfully fabricated using high-temperature rapid thermal annealing [1]. In this study, we present vertically stacked graphene junction diodes fabricated using direct bonding technique [2–4]. Figure 1(a) shows the schematic of a stacked graphene junction diode. Two graphene layers on SiC are directly bonded to each other. Gold–coated contact pins are attached to the graphene surface to establish ohmic contact. The graphene samples and contact probes are fixed by acrylic molds. Strong nonlinear current–voltage (I-V) characteristics are observed for this simple device configuration, as shown in Fig. 1(b). In the low bias voltage (Vb) region, the resistance of the graphene diode is approximately 20 GΩ. The current abruptly increases when the bias voltage is increased to approximately 30 V. The two-terminal resistance at a high bias voltage (100 V) is approximately 21 kΩ. The vertically stacked graphene junction exhibits bidirectional thyristor-type characteristics with a high on-off ratio of approximately 106. The Fowler–Nordheim (F-N) tunneling phenomenon is observed in the sub-threshold region. The gap distance estimated from the F-N plot is approximately 6 nm, which can be attributed to the large off resistance. The Coulomb force generated by applying the bias voltage causes the two graphene layers to attract each other, resulting in an electrically conductive state. The junction voltage (Vj) of the device was measured using a four-terminal configuration. As shown in Fig. 1(c), negative resistance is observed in the low-resistance region. The effective internal resistance of the junction diode is reduced to approximately 450 Ω. The off resistance of the diodes is considerably modified by the initial distance between the graphene layers. However, the I-Vj characteristics in the negative resistance region are identical for each device. This result suggests that the cause of the negative resistance phenomena is closely related to the band structure of graphene. A vertically stacked graphene junction diode with a high on-off ratio was demonstrated. The main component of the diode comprised a pair of single-crystal graphene layers fabricated through direct bonding. The negative resistance of the graphene diode presents new possibilities for the application of functional devices, such as terahertz emitters.[1] T. Aritsuki, et al., Jpn. J. Appl. Phys. 55 (2016) 06GF03.[2] J. Du, eta al., Jpn. J. Appl. Phys. 58 (2019) SDDE01.[3] N. Murakami, et al., Jpn. J. Appl. Phys. 60 (2021) SCCD01.[4] M. Ohi, et al., Jpn. J. Appl. Phys. 62 (2023) to be published. Figure 1

Ultraviolet-A electroluminescence from polymorphic CaSiO3:Ce3+ in electrolyte-thin film semiconductor

The realization of ultraviolet (UV) radiation lighting is emerging as a crucial method for water disinfection and particular fine matters. In particular, using UV sources as a small-scale disinfection option for water purification in remote areas is a growing trend. Herein, the study of UV electrolyte-assisted electroluminescence has been presetting by using Ce3+-activated polymorphic CaSiO3 as an emitting layer. It is prepared through an all-air atmosphere processes sol-gel-based spin coating method followed by a high-temperature rapid thermal annealing. Under an AC source in an aqueous electrolyte, the film is capable of emitting a UV-A spectrum attributed to the spin-allowed transition of Ce3+ ions. According to the spectrum, this device exhibits identical emission spectra in voltage and frequency dependency in AC sinusoidal driving voltage. With such a new method to obtain UV sources, this study could provide further development in silicon semiconductors, especially in the optoelectronics matter.

Stability and Failure Analysis of a W-Based Microhotplate

In this paper, we present the stability and failure of a tungsten-based microhotplate (W-MHP) fabricated with 0.5- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> standard CMOS technology. Resistance measurements and three-dimensional optical profilometer results combined with scanning electron microscopy observations were used to analyze the failure mechanisms of the W-MHP at operation temperatures up to 1000 °C. The electro-stress migration of the W film, recrystallization of the polycrystal W thin film, and breakage of the dielectric membrane were the dominant stability-failure mechanisms observed. The W-MHP had recoverable deformation and no evident resistance drift when the working temperature was below 450 °C. Correspondingly, at the operating temperature range of 500 °C– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$850~^{\circ }\text{C}$ </tex-math></inline-formula> , the W-MHP showed unrecoverable deformation and regular resistance drift caused by the electro-stress migration of the W heater and the interdiffusion of atoms between the W, Ti/TiN and SiO2. At temperatures higher than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1000~^{\circ }\text{C}$ </tex-math></inline-formula> , the recrystallization of the polycrystalline W film caused a sharp drop in resistance. In addition, sudden and large heat pulses were more likely to cause the suspended membrane to rupture, which resulted from the rapid accumulation of internal thermal stress and lack of time to release, indicating that the operating temperature of the MHP should slowly increase or decrease. One million cycles of thermal pulse between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25~^{\circ }\text{C}$ </tex-math></inline-formula> and 300 °C did not cause performance degradation of the device. Self-heating high-temperature rapid thermal annealing significantly improved the high-temperature stability of the MHP. [2022-0135]

Resonant Raman Scattering in Boron-Implanted GaN.

A small Boron ion (B-ion) dose of 5 × 1014 cm−2 was implanted in a GaN epilayer at an energy of 50 keV, and the sample was subjected to high-temperature rapid thermal annealing (RTA). The resonant Raman spectrum (RRS) showed a strong characteristic of a photoluminescence (PL) emission peak associated with GaN before B-ion implantation and RTA treatment. The PL signal decreased significantly after the B-ion implantation and RTA treatment. The analysis of temperature-dependent Raman spectroscopy data indicated the activation of two transitions in B-ion-implanted GaN in different temperature ranges with activation energies of 66 and 116 meV. The transition energies were estimated in the range of 3.357–3.449 eV through calculations. This paper introduces a calculation method that can be used to calculate the activation and transition energies, and it further highlights the strong influence of B-ion implantation on the luminesce of GaN.

Solid phase recrystallization induced by multi-pulse nanosecond laser annealing

The solid phase recrystallization of partially amorphized SOI structures using a pulsed Ultra-Violet Nanosecond Laser Annealing (UV-NLA) is reported. It is shown that combining UV-NLA process with a heating chuck at low temperature (450 °C) results in the perfect recrystallization of the amorphized portion of the silicon layer. Actually, sub-melt multi-pulse UV-NLA enables obtaining the total crystal recovery and a very high dopant activation rate, comparable to melt laser annealing approaches or high temperature rapid thermal annealing, with a very low overall thermal budget. This approach is a great alternative to traditional solid phase epitaxial regrowth process, which reach it limits, in terms of recrystallization rate, at temperatures lower than 500 °C. The process presented here is thus suitable for integration paths in which the thermal budget must be limited as for example 3D sequential integration. Besides the high activation rate, another benefit of the solid phase recrystallization, compared to an equivalent laser anneal in the melt regime, is the almost unchanged surface roughness. Furthermore, the use of an in-situ metrology based on Time Resolved Reflectometry (TRR) enables the monitoring of the crystalline seed thickness evolution during UV-NLA and the estimation of the recrystallization rate.

Direct transfer of thermochromic tungsten-doped vanadium dioxide thin-films onto flexible polymeric substrates

In this study, we demonstrate the preparation of flexible thermochromic vanadium dioxide (VO2) thin films via the direct film transfer technique using adhesive polymer films. Phase-change VO2 films are prepared via solution-based deposition using sub-stoichiometric colloidal VOx nanoparticles (NPs) on mica substrates; subsequently, a high-temperature rapid thermal annealing process is employed to induce phase transformation to monoclinic VO2 (VO2(M)). Thereafter, the direct film transfer of VO2(M) on mica substrates is conducted using PET substrates coated with an acrylate adhesive to form flexible and transparent mica/VO2(M)/PET films. The reversible phase transition behaviors of the flexible VO2(M) films are observed, such as a high luminous transmittance (Tlum > 50%) and solar modulation ability (ΔTsol > 15%). In addition, doping with tungsten ions systematically decreases the phase transition temperature (Tc) such that it is approximately equal to the ambient temperature, depending on the doping concentration. We observed that VO2(M) doped with 1.3 at% of W exhibits a Tc of 29 °C with Tlum and ΔTsol values of 53% and 10%, respectively; these are the highest Tlum and ΔTsol values reported thus far for flexible VO2(M) thin films at a near-ambient Tc.

Rapid Thermal Annealing for Surface Optimisation of ZnO Substrates for MBE-Grown Oxide Two-Dimensional Electron Gases

Two-dimensional electron gases (2DEGs) at the ZnO/ZnMgO interface are promising for applications in spintronics and quantum computing due to the combination of low spin-orbit coupling and high electron mobility. Growing high mobility 2DEGs requires high quality substrates with low impurity densities. In this work we demonstrate a ZnO substrate sample treatment combining high temperature rapid thermal annealing and chemical etching to improve the surface quality for the subsequent growth of 2DEGs. This process enables the growth of a 2DEG with low-temperature mobility of 4.8×104 cm2V−1s−1. An unannealed control sample shows a scattering rate at least three times greater than the annealed sample.

Toward production of diamond particles with improved fluorescence uniformity

Recent advancements in high temperature rapid thermal annealing (RTA) of irradiated diamond particles has made possible the production of the particles with fluorescence based on complexes of nitrogen and vacancies in a broad range of colors: blue, green, red/NIR as well as their mixtures, depending on the temperature and irradiation fluence. Still, the production of fluorescent diamond particles suffers from fluorescence inhomogeneity among particles. The goal of the current study is improvement of the fluorescence uniformity among the treated particles. Experiments were performed using as-grown 40 μm in diameter type Ib synthetic diamond particulate assuming that nitrogen uniformity among the as-grown particles should be higher versus milled ones used in previous studies. Particles were irradiated under mild conditions with 1 MeV electrons to a fluence 3 × 1018 e/cm2 without overheating during irradiation which resulted in relatively uniform green fluorescence among particles treated via RTA at temperatures corresponding to H3 centers formation.

Realizing High Thermoelectric Performance at Ambient Temperature by Ternary Alloying in Polycrystalline Si1-x-yGexSny Thin Films with Boron Ion Implantation

The interest in thermoelectrics (TE) for an electrical output power by converting any kind of heat has flourished in recent years, but questions about the efficiency at the ambient temperature and safety remain unanswered. With the possibility of integration in the technology of semiconductors based on silicon, highly harvested power density, abundant on earth, nontoxicity, and cost-efficiency, Si1-x-yGexSny ternary alloy film has been investigated to highlight its efficiency through ion implantation and high-temperature rapid thermal annealing (RTA) process. Significant improvement of the ambient-temperature TE performance has been achieved in a boron-implanted Si0.864Ge0.108Sn0.028 thin film after a short time RTA process at 1100 °C for 15 seconds, the power factor achieves to 11.3 μWcm−1 K−2 at room temperature. The introduction of Sn into Si1-xGex dose not only significantly improve the conductivity of Si1-xGex thermoelectric materials but also achieves a relatively high Seebeck coefficient at room temperature. This work manifests emerging opportunities for modulation Si integration thermoelectrics as wearable devices charger by body temperature.

(Invited) Proximity Gettering Design of Hydrocarbon Molecular Ion Implanted Silicon Wafers Using Direct Bonding Technique for Advanced CMOS Image Sensors: A Review

Complementary metal oxide semiconductor (CMOS) image sensors have become widely used ubiquitous devices such as smart phone and personal computer type tablets. Consumer markets strongly demands more high sensitivity imaging and more high speed image data processing for achieving advanced CMOS image sensor fabrication. However, there are some serious improvement technical issues in CMOS image sensor fabrication process. Extremely important technical issue is metallic impurity contaminated device active region during device fabrication process such as high temperature rapid thermal annealing, dry etching and plasma heat treatment. Metallic impurities formed deep energy level defects in the silicon band-gap. Thus, these deep energy level defects strongly affects electrical device characteristic such as pn-junction leakage current, recombination lifetime and gate oxide breakdown voltage. Another technical issue is oxygen impurity out-diffused to the device active region from a Czochralski (CZ) grown silicon substrate during device heat process. Oxygen impurity formed oxygen related deep energy level defects in the device active region of photo-diode space charge region and transfer transistor gate channel region. These oxygen related defects strongly influenced on electrical device performance such as image lag. Therefore, in recent years, CMOS image sensor manufacturers have strongly demanded silicon wafers with the highest metal and oxygen impurities gettering capability during CMOS device processes. In response, we have developed a novel gettering wafer production concept using a hydrocarbon molecular ion implantation technique for advanced CMOS image sensors [1][2][3]. This technique can implant a silicon wafer surface simultaneously with carbon and hydrogen elements that form the projection range using a hydrocarbon compound molecular gas source. In our previous study, it was found that a hydrocarbon molecular ion implanted silicon wafer had three unique characteristics for high performance of advanced CMOS image sensors. First, a hydrocarbon molecular ion projection range has high gettering capability of metallic impurities [1][2][4]. Second, this projection range also has a diffusion barrier effect for oxygen impurities out-diffusing to the device active region from a CZ grown silicon wafer substrate [5]. Third, it is expected that diffusing hydrogen to the device active region from the hydrogen of hydrocarbon molecular ions gettered in the projection range during the device fabrication process will have a passivation effect on unreconstructed surface dangling bonds and Si/SiO2 interface state densities such as local oxidation of silicon or shallow trench isolation [6][7]. Moreover, we achieved more improvement for gettering capability of hydrocarbon molecular ion implanted silicon wafer which formed epitaxial layer without epitaxial growth process using room temperature direct bonding technique. In this presentation, we demonstrate that a hydrocarbon molecular ion implanted silicon wafers using room temperature direct bonding technique has high gettering capability characteristics for transition metal and light element impurities such as oxygen, and hydrogen during the CMOS image sensor fabrication process.

Interfacial and electrical characteristics of tetragonal HfO2/Al2O3 multilayer grown on AlGaN/GaN

We report the study of HfO2/Al2O3 multilayer (HAOM) that is deposited on AlGaN/GaN heterostructure by plasma enhanced atomic layer deposition (PEALD). The properties and passivation effect of HAOM, sole Al2O3 and HfO2 films were investigated. After high-temperature rapid thermal annealing (RTA) of 850 °C, the formation of tetragonal phase in HAOM is presented. Al incorporates into HfO2 layers during RTA, which facilitates the formation of tetragonal HfO2. The HAOM film reveals an effective dielectric constant of ~ 30.2, a critical electric field of 7.6 MV/cm and leakage of only 6.8 × 10−4 mA/cm2 at gate bias of |Vg − Vfb| = 10 V. The HAOM insulating layer is shown to be effective in suppressing leakage current. In particular, the HAOM MIS diode current is reduced by both 6 orders of magnitude at negative bias of − 10 V and forward bias of 1.5 V compared with a conventional Schottky diode.

Effects of vacuum rapid thermal annealing on the electrical characteristics of amorphous indium gallium zinc oxide thin films

We investigated the effects of vacuum rapid thermal annealing (RTA) on the electrical characteristics of amorphous indium gallium zinc oxide (a-IGZO) thin films. The a-IGZO films deposited by radiofrequency sputtering were subjected to vacuum annealing under various temperature and pressure conditions with the RTA system. The carrier concentration was evaluated by Hall measurement; the electron concentration of the a-IGZO film increased and the resistivity decreased as the RTA temperature increased under vacuum conditions. In a-IGZO thin-film transistors (TFTs) with a bottom-gate top-contact structure, the threshold voltage decreased and the leakage current increased as the vacuum RTA temperature increased. As the annealing pressure decreased, the threshold voltage decreased, and the leakage current increased. X-ray photoelectron spectroscopy indicated changes in the lattice oxygen and oxygen vacancies of the a-IGZO films after vacuum RTA. At higher annealing temperatures, the lattice oxygen decreased and oxygen vacancies increased, which suggests that oxygen was diffused out in a reduced pressure atmosphere. The formation of oxygen vacancies increased the electron concentration, which consequently increased the conductivity of the a-IGZO films and reduced the threshold voltage of the TFTs. The results showed that the oxygen vacancies and electron concentrations of the a-IGZO thin films changed with the vacuum RTA conditions and that high-temperature RTA treatment at low pressure converted the IGZO thin film to a conductor.

Effect of high temperature rapid thermal annealing on optical properties of InGaAsP grown by molecular beam epitaxy

The effect of rapid thermal annealing (RTA) on the optical properties of InGaAsP with band-gap energy of around 1.05 eV for quadruple-junction solar cells grown by molecular beam epitaxy (MBE) has been investigated. The photoluminescence (PL) spectrum of InGaAsP film annealed at 800 °C has strong integrated intensity and low activation energy of band-tail states. The time-resolved PL measurement shows that the decay time of the InGaAsP annealed at 800 °C and as-grown one are 11.6 ns and 3.0 ns at 10 K, respectively. An S-shape PL decay time as a function of temperature for the InGaAsP annealed at 800 °C is observed and is explained by the carrier relaxation dynamics. The RTA process induces reorganization of In and Ga inside the alloy due to the existence of miscibility gap in InGaAsP grown by MBE owing to the Be diffusion at high temperature and results in an increased composition uniformity and an improved PL intensity.

Carbon effect on the survival of vacancies in Czochralski silicon during rapid thermal anneal

Rapid thermal anneal (RTA) at high temperatures can be employed to introduce vacancies to control oxygen precipitation (OP) behavior in Czochralski (CZ) silicon. Such excessive vacancies survive from the recombination of silicon-interstitials and vacancies (V-I recombination) during the RTA. In this work, we aim to elucidate the carbon effect on the survival of vacancies in CZ silicon during the high temperature RTA by means of gold diffusion in combination with deep-level transient spectroscopy. It is revealed that the existence of ∼1017 cm−3 carbon atoms significantly increases the amount of survival vacancies in the form of vacancy-oxygen (VOm, m ≥ 2) complexes in CZ silicon when subjected to the 1250 °C/60 s RTA. Moreover, such an increase in the number of vacancies becomes more significant with the increase in the cooling rate of RTA. The density functional theory calculations suggest that the V-I recombination is to some extent unfavorable as a carbon atom is close to the silicon-interstitial. Alternatively, it is believed that the substitutional carbon (Cs) atoms tend to trap the silicon-interstitials, thus forming Ci complexes (Cs + I → Ci) in CZ silicon during the RTA. In this context, the V-I recombination is suppressed in a manner, leading to the survival of more vacancies, thus generating more VOm complexes. Furthermore, after the 1250 °C/60 s RTA, the oxide precipitate nucleation based on the VOm complexes is more significant in carbon-rich CZ (CCZ) silicon than in the conventional CZ counterpart. Hence, when subjected to the same OP anneal consisting of the nucleation anneal at 650 or 800 °C for 4 h and the subsequent growth anneal at 1000 °C for 16 h, CCZ silicon possesses a higher density of bulk microdefects and therefore stronger internal gettering capability than CZ silicon. However, the nucleation temperature for OP should be carefully selected as 650 °C for CCZ silicon in order to form an oxide precipitate-free denuded zone.

Study on defect annealing potential and bulk micro defect formation using high temperature RTA conditions for Cz‐grown silicon

In this paper, the key parameters of a rapid thermal annealing (RTA) nitriding step are discussed with respect to vacancy‐ and oxygen precipitate (BMD)‐profile formation. These RTA key performance parameters are the maximum NH3 dissociation temperature (i), the temperature stability of the stored vacancy peak (ii), and the defect dissolution capability of self Si agglomerates at elevated temperatures (iii). This parameter study could be helpful for a future model of the vacancy in‐diffusion process into the Si near surface region. Especially the gate oxide integrity (GOI) is an important parameter to establish long life cycles in current memory devices. After NH3 RTA processing, it was surprisingly found that the GOI defect level is still influenced by small‐sized grown in particles. It is demonstrated that a complete restoration toward a high GOI signal can be achieved via a 1300 °C RTA step. The gate oxide integrity is afterwards as good as observed on a defect free polished CZ wafer.

Influence of rapid thermal annealing on electrical and structural properties of Pd/Au Schottky contact to Ga-polarity GaN grown on Si (111) substrate

Abstract We studied the effect of high temperature rapid thermal annealing on the electrical and structural properties of Pd/Au Schottky contact to Ga-polarity GaN grown by MBE on p-Si substrate. Current-voltage (I-V), capacitance-voltage (C-V), X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD) and atomic force microscopy (AFM) measurements are performed for the electrical and structural characterization of the Schottky diode. It has been observed that there is a significant improvement in barrier height and ideality factor with reduction in leakage current upon annealing. The estimated Schottky barrier height (φ B0 ) for the as-deposited contact is 0.61eV (I-V) and 0.94 eV (C-V). While, the extracted barrier height for 700 °C annealed contact is improved to 0.74 eV (I-V) and 1.09 eV (C-V). In addition, the surface state density is calculated using C-V and it is found that there is ten time reduction in surface state density for 700 °C annealed Pd/Au Schottky contact compared to the as-deposited Schottky contact to semiconductor. X-ray photoelectron spectroscopy (XPS) depth profile results showed that there is out diffusion of Ga into metal film which may have formed metal-gallide phases for the annealed Schottky contacts that was confirmed by X-ray diffraction (XRD) results. It implies a reduction in nitrogen related vacancies and dangling bonds associated with GaN, which could be the reason for increase in the Schottky barrier height. Moreover, the surface morphology of the contacts is analysed by atomic force microscopy (AFM) and it is found that the surface roughness of Schottky contact does not degraded upon annealing. This indicates that the contacts were thermally stable during annealing.

Impact of crystalline damage on a vertically integrated junctionless nanowire transistor

The influence of process-induced defect formation was investigated in a vertically integrated (VI) junctionless-mode field-effect transistor (JL-FET). Compared to the low energy and one-time ion-implantation process to fabricate a single nanowire-based FET, the high-energy and repetitive ion-implantation process for the creation of the VI JL-FET inevitably generates more defects in the crystalline sites. Even after high-temperature rapid thermal annealing, the non-recovered defect sites existing in the interface and silicon channel, as verified by a transmission electron microscopy analysis, lead to the degradation of the electrical performance such as on- and off-state current. Particularly, the abnormal behavior of the off-state current, mostly arising from the gate-induced drain leakage, was analyzed using the experimental results, and supported by the numerical simulation as well.

Effects of high-temperature rapid thermal annealing for seed layers on the crystallographic evolution in hydrothermal ZnO nanostructures

In this work, we investigated effects of high temperature rapid thermal annealing for the zinc oxide (ZnO) seed layers on the growth morphology and crystal orientation of hydrothermal ZnO nanorods (NRs). The seed layers were prepared by sol–gel spin coating and annealed by two-step rapid thermal processes at different peak temperatures ranging from 600 to 900°C for a short time period of 1min. The seed layers annealed in a temperature range of 600–800°C were all polycrystalline; however, they exhibited a highly Zn-deficient amorphous state when annealed at 900°C as observed by X-ray photoelectron spectroscopy, X-ray diffraction (XRD), and cross-sectional transmission electron microscopy (TEM). The vertical NRs normal to the substrate were grown along [001] direction atop the polycrystalline seeds annealed at 600–800°C, whereas different growth morphology of flower-like NRs was observed on the seeds annealed at 900°C with the strongest XRD peak along the [100] orientation. From our cross-sectional TEM analysis, this flower-like architecture was initiated from the pioneer crystals laterally grown along [001] direction guiding the subsequent growth of petal NRs oriented by a slight difference in growth direction.

Charge storage phenomenon derived from composition redistribution for single Hf0.8Si0.2Ox film after high-temperature treatment

Simple metal-Hf0.8Si0.2Ox-silicon capacitors have been fabricated. It is observed that the capacitor after high-temperature rapid thermal annealing treatment exhibits a significant charge storage phenomenon, with large hysteresis windows of 3.93 V in a ±8 V gate sweeping voltage range, faster operating speed and good data retention characteristics. The occurrence of charge memory should be attributed to the high-temperature treatment, which gives rise to the HfO2 crystallization and elemental composition redistribution in the Hf0.8Si0.2Ox film, forming a typical metal-oxide-high-κ-oxide-silicon memory structure. Therefore, the high-temperature treatment that induced the internal structure transformation is an appealing approach, and provides a guide for future charge-trap memory design.

Thermal Behavior of Residual Defects in Low-Dose Arsenic- and Boron-Implanted Silicon After High-Temperature Rapid Thermal Annealing

We investigated the thermal behavior of defects remaining in low-dose (<;10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) arsenic- and boron-implanted Si after high-temperature (1100 °C) rapid thermal annealing (RTA). The defects remaining after RTA were characterized as vacancy-type defects, and confirmed to be created by nonequilibrium states that occur during the extremely rapid cooling step of the RTA sequence. They were gradually removed by applying additional furnace annealing (FA) (i.e., thermal equilibrium heating process) at 300-400 °C. At the range of 500-600 °C, however, carbon- and oxygen-related point defects were newly created. These defects were confirmed to be eliminated at 700 °C, and the crystal quality was significantly improved. When using a rapid thermal process for heat treatment after low-dose impurity implantation, it is necessary to apply an equilibrium thermal treatment at >700 °C to remove residual damage as well as to activate impurities.