High Temperature Operating Life Test Research Articles

High reliability of piezoresistive pressure sensors by wafer to wafer direct bonding at room temperature

As a micro-component for detecting and acquiring pressure data, piezoresistive pressure sensors are widely used in the microelectronic industry. Enhancing the sensitivity and reliability of piezoresistive pressure sensors can be achieved with optimized fabrication process and advanced techniques. However, in previous studies, there is limited information and knowledge of the relationship between the sensor performances and their fabrication process. In this study, we further optimized the fabrication process for piezoresistive pressure sensors, achieving a significantly higher stability of the pressure sensor compared with that of the commercial products obtained based on the standard test of “Pressure & High temperature Operating Life Test.” A detailed analysis revealed that both the designed structure of the piezoresistive pressure sensor and the preliminary thermal treatment conditions for tetraethylorthosilicate (TEOS) oxide substrate are critical factors that contribute to the improved performance of the pressure sensors. After low-temperature annealing, the atomic scale characterization of the interfaces between different material layers of the sensor showed well-proportioned interfaces. Furthermore, reducing water content in the sensors through high-temperature annealing is crucial for improving the stability of the piezoresistive pressure sensors.

Test Method and Application of High-Temperature Operating Life of Automobile Chips

The high temperature operating life (HTOL) test is an important item in the reliability test of automobile chips. The goal of the HTOL test is to evaluate the durability of automobile chip products under high-temperature loads. Based on the common-used standards, calculation models, and related research experience of evaluating the reliability of electron devices at home and abroad, this paper focuses on the model of the high-temperature durability test model of automobile chips and analyzes different factors affecting the high-temperature operating life test. The general calculation and analysis model and method of the high-temperature operating life test of automobile chips are presented in this paper, which provides a reference for determining the indicators of the high-temperature operating life test of automobile chips.

Dynamic high temperature operating life test methodology for long-term switching reliability of GaN power devices

Dynamic High Temperature Operating Life (DHTOL) test is becoming a mandatory test for GaN power devices as it explores the device reliability under application-close conditions. However, the number of applications and circuitries where GaN power devices are intended to be used poses a serious challenge in terms of validity of the application-like test setup used to evaluate the device degradation. In this paper, an accurate model supported by real DHTOL tests was developed precisely including test board and device properties with parasitic elements providing an advanced environment to support the evaluation of the GaN switching behavior and its stability. In order to evaluate and validate the current and voltage peaks, which define the switching stress conditions, we present the methodology to extract device, package, and board parasitics of the complete test setup. Furthermore, an accurate junction temperature (TJ) estimation and prediction technique is also presented being essential to judge and discriminate the natural self-heating effects from the one induced by the RDSON degradation during long-term repetitive hard-switching events.

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.

Research on lumen depreciation related to LED packages by in-situ measurement method

In this paper, lumen depreciation of LED in reliability experiment was monitored by in-situ measurement method. The partial LED flux on the receiving surface of fiber cable was captured, and it was proportional to the total luminous flux of LED light source when we provided an exact distance. The high temperature operating life test was used to find the weakness elements of LED packages with a limiting maximum temperature stress of 125°C. Four kinds of packaged samples were constituted with difference components, and the lumen depreciations were presented. Combined with the lumen depreciation data and sampling inspection, the results could be summed up as follows: (i) the luminous flux of LED chip had a steady and slow depreciation, however, that of the samples coated with the phosphor–silicone composites had an initial sharp decline and then reach the stable state. (ii) The samples of only chip encapsulated by silicone and those of commercial white LEDs were carbonized on the center surface between chip and materials of encapsulant. As a conclusion, the silicone as an LED encapsulant could induce flaws, the material properties in larger coefficient of thermal expansion (CTE) and stronger adhesion should be considered in the package design stage, and the degradation of phosphor–silicone composites led to a fast light energy loss during the initial high temperature aging test, and then reached up to steady.

Degradation Mechanisms of Mid-Power White-Light LEDs Under High-Temperature–Humidity Conditions

More and more mid-power white-light LED (MP LED) solutions have been used in outdoor illumination due to their good performance, cost attractiveness, and low energy consumption as compared with conventional lighting solutions. Hence, there is a need for MP LED manufacturers to develop more robust MP LEDs aimed at outdoor applications but still offer a significant cost benefit as compared with currently widely used high-power LEDs. This implies that MP LEDs would be operated in an environment with high humidity and high temperature. This may lead to serious degradation with different failure modes compared with an indoor operation. However, the combined effect of temperature and humidity on the MP LED reliability has not been extensively studied in literature. In this paper, MP LEDs were studied by the wet high-temperature operation life (WHTOL) test in order to understand their degradation mechanisms due to the combined effect of temperature and humidity. It is found that encapsulant discoloration (yellowing) is the major degradation mechanism in the WHTOL test, which will induce serious lumen degradation and color shift. Furthermore, it has been found that electrical degradation in terms of forward voltage increase will also affect the lumen maintenance. Finally, statistical analysis shows that lumen degradation mechanisms in the WHTOL test are similar to a failure in the LM-80-08 test, demonstrating that the WHTOL test is an efficient accelerated degradation test method, which dramatically reduces the test duration compared with the LM-80-08 test.

Electrical and Reliability Performance of Molded Leadless Package for High-voltage Application

This paper investigates the influence on electrical and reliability performance of molded leadless package for high-voltage power integrated circuit application. Semiconductor devices are mostly encapsulated by using epoxy molding compounds which act as protection for the ICs from damage to the harsh environment. Quad Flat No Lead was selected since the application requirement for compact AC to DC portable adapter charger and more input and output pin. High-voltage package was designed based on the IPC-2221 standard specification and creepage distance was calculated under external component lead, uncoated. Two epoxy molding compounds were used namely as type A and B. Key properties of EMCs were identified such as ionic content, glass transition temperature and volume resistivity. The electrical tested at room temperature on high-voltage leakage current at 700V showed EMC B has no failure compared with EMC A. On top of that, electrical parametric distribution showed that the Cpk of EMC B was extremely robust compared with EMC A. Reliability test was conducted for high temperature operating life test at 115˚C and EMC B was passed up to 1000hours while EMC A was failed. Meanwhile, High Temperature Storage Life test at 150˚C and Temperature Humidity Bias Test at condition 85˚C, 85% relative humidity showed that EMC B was passed for 1000hours but EMC A was failed at 168hours. However, both compounds A and B were passed delamination criteria tested by scanning acoustic tomography technique before and after subjected to moisture sensitivity level 1.

Reliability Study of Silver, Copper and Gold Wire Bonding on IC Device

Copper wire bonding in IC packages is not always suitable for devices with active circuit under bonding pad because higher bonding power required for copper wire bonding may cause top aluminum metal splash and mechanically impact the circuit underneath. Silver wire is an alternative solution to this problem based on its physical properties and lower cost compared to gold wire. Ag88%Au8.5%Pd2.5%X1% and Ag95%Au1.5%Pd2.5%X1% alloyed silver wires are used in the study to compare with copper and gold wires of 99.99% in purity. As bonding power plays a dominating role in wire bonding, we focused on the effects of silver, copper and gold bonding wires with different bonding power on the top aluminum metal splash of power device by Optical Microscope(OM) and Scanning Electron Microscope(SEM). The ball shear strength of the bonding wires with different bonding power in samples without mold compound encapsulation was investigated before and after 24, 48, 96 and 192 hours of pressure cooker test (PCT). The intermetallic compound (IMC) formed between silver and aluminum was confirmed by focus ion beam (FIB) and transmission electron microscope (TEM). Although the top surface of the silicon device shows no significant difference after aluminum layer removal for all three wire types, the severity level of vertical deformation and side splash of aluminum layer due to copper wire bonding is much more than silver or gold wire using same amount of bonding power. Ball shear strength of non-encapsulated silver wire decreases dramatically after PCT aging compared with copper wire or gold wire and some samples show zero shear strength after PCT 96 hours and PCT 192 hours for silver wires doped with Pd/Au. Furthermore, larger bonding power induces higher ball shear strength. The major IMC compositions between silver and aluminum are Ag3Al and Ag2Al. A thermo dynamic model was built to explain why silver wire is prone to corrosion compared with copper wire by humidity although copper is easier to be ionized than silver. No electrical test was performed as the samples cannot be tested without package encapsulation and singulation. Furthermore, silver wire samples in SO8 package with mold compound encapsulation were subjected to highly accelerated stress test (HAST), PCT, temperature cycle test (TCT) after MSL1 preconditioning test as well as high temperature operation life test (HTOL) according to JEDEC procedures. The encapsulated samples using either Ag 88wt% or Ag95wt% alloys all passed MSL1 and PCT/HAST/TCT/HTOL. Drain to source on-resistance (Rdson) of the device including package parasitics was measured and it has no significant difference between silver wire and gold wire. The results from this study shows promising data using silver alloy wires but care should be taken to further understand the degradation of silver-aluminum interface under severe humidity condition. Using other metallization on silicon top surface such as NiAu or CuAu can significantly alleviate the interface problem related to AgAl.

Impact of Epi-Layer Quality on Reliability of GaN/AlGaN/GaN Heterostructure Field-Effect Transistors on Si Substrate

This paper reports the impact of epi-layer quality on the short-term reliability of GaN/AlGaN/GaN heterostructure field-effect transistors fabricated on Si substrates. At an early stage of 50 V high-temperature operating life tests, they exhibited a significant lowering of the forward breakdown voltage. The mean time to failure (MTTF) determined by this degradation mode was exponentially increased by decreasing full-width at half-maximum (FWHM) values of X-ray rocking curves. In small FWHM samples, extrapolated MTTF values exceeded 1×107 h at Tch=150°C. Alternatively, another degradation mode such as drain current degradation will dominate the long-term reliability at this temperature range. High-resolution transmission electron microscope and energy dispersive X-ray spectroscopy analyses revealed thinning or partial vanishment of GaN cap layer in a degraded sample. Gate current-voltage characteristics calculation based on the self-consistent Schrodinger-Poisson analysis suggested lowering of the effective barrier height by decreasing cap layer thickness is responsible for the Schottky degradation. When considering these experimental and theoretical findings, degradation mechanisms assuming diffusion of interfacial materials along dislocations are discussed.

Importance of multi-temp testing in automotive qualification and zero defects program

For automotive qualification of Integrated circuits (ICs), multi-temp testing is required by AEC-Q100. In this paper, we demonstrate the importance and necessity of this multi-temp testing in automotive qualification and zero defects program. During the qualification of one of our new products, we found that all samples could pass electrical testing at room temperature after high temperature operating life test, but a few of them failed at hot temperature. One transistor in the circuit was found to have large leakage current. Only at hot temperature, this leakage current was increased (>50 μA) and the fail was detected during hot electrical testing. Root cause was identified and design error is corrected before the release of the product. No failures are observed anymore.

Effect of Test Conditions on Electromigration Reliability of Sn-Ag-Cu Flip-Chip Solder Interconnects

The high-temperature operation life test (HTOL) was conducted in this paper to study electromigration phenomena of solder interconnects in a flip-chip package assembly. We examined the fatigue reliability and morphological patterns of three solder compositions: Sn-4Ag-0.5Cu, Sn-3.5Ag-1Cu, and Sn-3Ag-1.5Cu, subjected to two test conditions consisting of different average current densities and ambient temperatures (5kA∕cm2 at 150°C and 20kA∕cm2 at 30°C). It is interesting to realize that as the Cu weight content of the solder composition increases, the fatigue life increases under 5kA∕cm2 at 150°C but decreases under 20kA∕cm2 at 30°C. Observed electromigration morphologies along with computed current density and temperature distributions on solder interconnects from the electrothermal coupling analysis were examined, correlated, and discussed.

Effects of pre-bump probing and bumping processes on eutectic solder bump electromigration

This paper investigates the electromigration reliability of flip chip packages with and without pre-bump wafer probing via high temperature operation life test (HTOL) using printed and electroplated bumps. Under bump metallization (UBM) of printed and electroplated bumps is a thin film of Al/Ni(V)/Cu and Ti/Cu/Ni, respectively, while the bump material consists of eutectic Sn/Pb solder. Current densities from 7380 to 20 100 A/cm 2 and ambient temperatures at 100, 125 and 150 °C are applied in order to study their impact on electromigration. The results reveal that the bump temperature has a higher influence than the current density when it comes to bump failures. The observed interconnect damage is from bumps with electrical current flowing upward into the UBM/bump interface (cathode). Identified failure sites and modes reveal structural damage at the region of the UBM and UBM/bump interface, in the form of solder voiding and cracking. The effects of current polarity, current crowding, and operation temperature are key factors to electromigration failures of flip chip packaging. The maximum allowable current density of the electroplated bumps is superior to the printed bumps by a factor of 3.0–3.7 times. Besides, the median time to failure (MTTF) of without-underfill packaging is preferred to that of with-underfill packaging by 1.5–2.2 times. Furthermore, the differences in MTTF between pre-bump and without pre-bump probing procedures are 2.0–19.4% and 1.6–10.3% for printed and electroplated bumps, respectively.

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm 2 and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.

Conversion of the under bump metallurgy into intermetallics: the impact on flip chip reliability

In high temperature applications, the conversion of the under bump metallurgy (UBM) into UBM-Sn intermetallics can ultimately limit the reliability of flip chip components. Here, an intermetallic growth model characterizing the rate of electrical failure to the rate of UBM consumption is developed which derives a relationship between field reliability and accelerated temperature tests. For a flip chip structure employing eutectic Sn/Pb solder joined to Ni(V), bump shear and temperature storage were then used in concert with temperature cycling or high temperature operating life tests to evaluate the interaction of UBM loss with respect to electromigration and solder fatigue. In this way, field life was estimated for a given set of conditions: mechanical loading, temperature, temperature gradients, and applied current. While shear testing proved a poor indicator of bump reliability, a modified bump shear technique allowed a simple visual method for monitoring the amount of UBM consumption following accelerated testing. A seemingly unimportant variable, the surface finish of the substrate, was found to play a significant role in determining the rate of intermetallic growth, and hence, impacted the overall reliability. In particular, the incorporation of small amounts of gold into the solder joint during assembly reflow of gold finished substrates influenced the reaction of Ni into SnNi intermetallics. The role of gold, the impact on reliability, and potential corrective actions are discussed.

Impact of ESD-induced soft drain junction damage on CMOS product lifetime

The impact of ESD-induced soft drain junction damage on product lifetime was investigated. Several thousand input-output (IO) pads of a 0.35 pm CMOS IC were stressed by ESD (electrostatic discharge) and subsequently subjected to bakes, ESD re-stress and high temperature operating life tests. While the ESD-induced soft drain junction damage appears to be stable versus temperature stress and ESD-re-stress, it results in early failures during accelerated operating life tests. These lifetest failures are caused by breakdown of the gate oxide which was left unbroken during the ESD stress that caused the ESD-induced soft drain junction damage. Thus, ESD-induced soft drain junction damage might cause a reliability risk (latent ESD failure). Consequently, it needs to be avoided by assuring a sufficient robustness of the IC against this ESD damage mechanism. A leakage current criterion of I VA is rather large to detect this kind of damage after ESD stress.

Temperature acceleration of CMOS IC operating life

We carried out the high temperature operating life test (HTOT) of CMOS ICs which include n-channel ROMs which were contaminated deliberately by leaving naked for a long time in the room ambient before moulding and got the bimodal failure distributions consisting of m = 0.3–0.5 and m = 2.6–3.3 parts in the Weibull chart. At the same time, the activation energy of 1.14 eV was obtained for m = 2.6–3.3 parts. In order to make clear the failure mechanism of the latter part, we made the test devices for detecting channel leakage current (abbrev. TEG) and checked the shift of leakage current and life acceleration due to temperature in HTOT. Then we found that leakage currents of TEGs have an incubation time, their activation energy was nearly equal to that of the CMOS ICs above and m = 2.6–3.3 for CMOS ICs were reasonably explained due to the gradient α of the logarithm of the median leakage current to that of time. Also we got a 40 times longer life for the same CMOS ICs coated with Si 3N 4 film instead of SiO 2. And finally, from these data, we could verify the cause of failure in CMOS ICs.

Analysis of integrated circuit failure modes and failure mechanisms derived from high temperature operating life tests : R. A. Vetter. IEEE 11th Annual Proceedings Reliability Physics (1973). p. 133

Analysis of integrated circuit failure modes and failure mechanisms derived from high temperature operating life tests : R. A. Vetter. IEEE 11th Annual Proceedings Reliability Physics (1973). p. 133