High Speed Vedic Multiplier Research Articles

Design and Simulation of Vedic Multiplier Using Verilog HDL

Abstract: This Paper is created for the simulation of a high speed Vedic multiplier. In the proposed paper, the multiplier circuit is designed by using algorithms that involve Vedic Mathematics. Calculations that involve Vedic mathematics are derived from the old contexts known as Vedas. The VHDL programs are synthesized and simulated using Xilinx ISE simulator. The study of Vedic multipliers is done in comparison with the conventional multipliers to find the fact that which multiplier is fast and efficient and the research and analysis has shown that the Vedic multiplier is more efficient than conventional multipliers because of its fast response in digital signal processing and it gives less delay in system logic design. Vedic mathematics used in the Vedic multiplier increases the speed of multiplier as it reduces the number of partial products. Hence, the speed of the overall digital design can be increased by implementing a Vedic multiplier.

Comparative Analysis of Vedic Multiplier using Various Adder Architectures

The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, different adder topologies like Carry Look ahead Adder, Kogge Stone Adder, Carry Skip Adder are used to compare area, delay and power. The reviewed methods are implemented on 45nanometer(nm), 90nm and 180 nm CMOS technology. The results of all the prior approaches are reviewed and an efficient method out of them has been proposed.

Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

Design and investigation of low-complexity Anurupyena Vedic multiplier for machine learning applications

The current world of computers is based on machine leaning and profound learning towards artificial intelligence. In recent investigations, parallelisms are used to solve difficult problems. For the implementation of the FPGA, new architectures have been built using design techniques VLSI and parallel computing technologies. Research on reconfigurable computing, machine learning and signal processing should be constantly monitored in the development of artificial intelligence. Energy-restricted computer devices should be continuously developed to support algorithms in the machine learning process. In machine learning algorithms, multipliers and adders play a significant role. In ALU, Convolutionary Neural Network (CNN) and Deep Neural Networks (DNN), the multiplier is an energy-consuming factor of signal processing. In this project, for the DNN, the high-speed Vedic multiplier has been introduced. The versions of the parallel–parallel (PP), serial–parallel (SP) and two-speed (TS) multipliers are compared to the standard 64-, 32- and 16-bit models. The results are obtained for an Intel Cyclone V 5CSEMA5U23C6 FPGA, using the Intel Quartus 17.0 software suite.

Design of a high speed Vedic multiplier and square architecture based on Yavadunam Sutra

In current day situation we come across numerous mathematical challenges. This could be overwhelmed by the Vedic Mathematics. Vedic Mathematics is an ancient approach to solve problems in a rapid manner. In this paper the design of a novel Vedic square and multiplier architecture based on Yavadunam Sutra is proposed. Yavadunam is a squaring sutra of the Vedic Mathematics. We have designed a generic architecture for this squaring sutra and have designed a high speed Vedic binary multiplier architecture using the principles of Yavadunam sutra. The proposed multiplier offers significant improvement in speed. Xilinx Spartan FPGA is used to design and realize the architecture and the Synopsys device with 90 nm and 180 nm technology is used to synthesize the same.

A 16X16 High Speed Vedic Multiplier for Area and Power Reduction

A 16X16 High Speed Vedic Multiplier for Area and Power Reduction

Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate (MAC) and inner product are some of the frequently used operations in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors in its arithmetic and logic unit. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications. In this project, the comparative study of Vedic multiplier and Sequential multiplier is done for low power requirement and high speed. The proposed architecture is based on the Vertical and Crosswise algorithm of ancient Indian Vedic Mathematics, which increases the speed of multiplier by reducing the number of clock cycles thus achieving the greater speed of the processor or system.

Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device

Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.

Design and implementation of 4-bit Vedic Multiplier

Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance .The need of high speed multiplier is increasing as the need of high speed processors are increasing . A Multiplier is one of the key hardware blocks in most fast processing system which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction.

Design of High Speed Vedic Multiplier based on Nikhilam Sutra Algorithm using Successive Approximation

The mathematical system followed in the Ancient India is Vedic Mathematics. It helps to calculate the arithmetic operations faster without any computerized system. Vedic Mathematics works on the principles of Sutra. It deals with mathematics linked with arithmetic, algebra, and geometry. These modus operandi and ideas can be directly applied to trigonometry, plain and spherical geometry, conics, differential calculus, integral calculus and applied mathematics of different kinds. There are various multipliers among them Urdhva Triyakbyam Sutra is used widely because it dissipates less power and area efficient multiplier. Nikhilam sutra is not widely used due to its limitations in the calculation of remainder. In this paper, high speed Vedic multiplier is designed by modifying Nikhilam sutra principles using bit reduction technique. In the calculation of remainder in Vedic multiplier based on Nikhilam Sutra, the addition and subtraction is done with the base value of 10 for decimal number system. For binary multiplication, base 2 is considered and 2’s complement is taken to derive the remainder in the algorithm. In this work, the remainder is calculated using bit reduction technique to reduce the complexity of the multiplier. The first two bits are reduced from the given N-bit number. Hence, the multiplier size is reduced to N-2 for remainder multiplication. Additionally, shift operations are needed to perform the multiplication of two N-bit binary numbers. By the successive application of this multiplier, higher bit length multiplier can be easily designed with less computation time. The proposed algorithm is implemented using mentor Graphics tool. The results are compared N-bit conventional multipliers and the proposed method. Comparing with conventional methods, the Wallace multiplier is the fastest multiplier. While comparing with conventional Nikhilam multiplier and Urdhva Triyakbyam multiplier, our proposed multiplier gives the result in minimum computation time. While comparing with Wallace and our proposed gives the optimum result. The proposed design is suitable for high speed compact size arithmetic applications.

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Design and FPGA Implementation of High Speed Vedic Multiplier

is an operation much needed in Digital Signal Processing for various applications. This paper puts forward a high speed Vedic multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra from Vedic Math for multiplication and Kogge Stone algorithm for performing addition of partial products and also compares it with the characteristics of existing respective algorithms. The below two algorithms aids to parallel generation of partial products and faster carry generation respectively, leading to better performance. The code is written in Verilog HDL and implemented on Xilinx Spartan 3 and Spartan 6 FPGA kit using Xilinx ISE 9.1i. The propagation delay of the implemented architecture is obtained to be 28.699ns and 15.752ns respectively.

High Speed Vedic Multiplier in FIR Filter on FPGA

High Speed Vedic Multiplier in FIR Filter on FPGA

FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics.

FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics.

An Improved Squaring Circuit for Binary Numbers

In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.

High Speed Vedic Multiplier for Digital Signal Processors

Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among the various methods of multiplications in Vedic mathematics, Urdhva tiryakbhyam is discussed in detail. Urdhva tiryakbhyam is a general multiplication formula applicable to all cases of multiplication. This algorithm is applied to digital arithmetic and multiplier architecture is formulated. This is a highly modular design in which smaller blocks can be used to build higher blocks. The coding is done in VHDL (very high speed integrated circuits hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the modified Booth Wallace multiplier which is a fast multiplier. This Vedic multiplier can bring about great improvement in DSP performance.