An Improved Squaring Circuit for Binary Numbers

Kabiraj Sethi,Rutuparna Panda

doi:10.14569/ijacsa.2012.030220

Abstract

In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.

Highlights

Multiplication and squaring are most common and important arithmetic operations having wide applications in different areas of engineering and technology
In order to calculate the square of a binary number, fast multipliers such as Braun Array, Baugh-Wooley methods of two’s compliment, Booth’s algorithm using recorded multiplier and Wallace trees are in use
This paper discusses a possible application of Vedic mathematics to design multipliers and squaring circuits

Summary

INTRODUCTION

Multiplication and squaring are most common and important arithmetic operations having wide applications in different areas of engineering and technology. This paper discusses a possible application of Vedic mathematics to design multipliers and squaring circuits. Authors of [15] have shown the effectiveness of this Sutra to reduce N×N multiplier structure into an efficient 4×4 multiplier structure They have mentioned that 4×4 multiplier section can be implemented using any efficient multiplication algorithm. A squaring circuit has been reported in the literature [19] This may be noted that designing Vedic multipliers using array multiplier structures as discussed in above references provide us less delay and, they are treated as high speed multipliers as compared to Booth’s algorithm using recorded multipliers and Wallace trees. One more crucial issue with the earlier proposed methods is that they use four numbers of such Vedic multipliers to evaluate squaring of a n-bit binary number.

THE MULTIPLIER ARCHITECTURE

VERIFICATION AND IMPLEMENTATION

CONCLUSION