High-speed SRAM Research Articles

Design and Implementation of High Speed SRAM Cell

Static Random Access Memory's main design goals are to have a consuming low power and high speed, as technology is developing at a faster paceand this has given rise to new challenges.The high speed along with stability of SRAM are important issues to improve efficiency and performance of the system. This proposed work presents design and implementation of 1Kb 6T SRAM using CMOS technologies by using EDA tool. In this proposed work, SRAM’s cell is operated in 1V voltage. Our proposed high speed SRAM consisting 6T achieved read delay and write delay of 29.4ps & 15ps respectively. And also our designed cell has stability of 70 mV & 195 mV for read SNM and write SNM respectively

DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks.

This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply-Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.

Up to 45% Faster Supply Boosted Voltage Sense Amplifier (SBVSA) for High-Speed SRAMs

Up to 45% Faster Supply Boosted Voltage Sense Amplifier (SBVSA) for High-Speed SRAMs

Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications

Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications

Efficient BCH Code Encoding and Decoding Algorithm With Divisor-Distance-Based Polynomial Division for STT-MRAM

Error-correcting codes (ECCs) are important and widely implemented in memories from high-speed SRAM cache to high-volume 3D-NAND. However, from the viewpoint, ECC technology of Spin-transfer torque magnetic random-access memory (STT-MRAM) is not established yet, as the operation speed of STT-MRAM is higher than DRAM/3D-NAND, and its volume is larger than SRAM. Moreover, it is difficult for existing ECCs to guarantee low latency and low hardware complexity while achieving high error correction capabilities. In this work, the time efficiency of both encoding and decoding of Bose-Chaudhuri-Hocquenghem (BCH) codes for STT-MRAM is optimized. A divisor-distance-based (DDB) polynomial division method is proposed to accelerate the polynomial division of BCH encoding and decoding. The DDB division method leverages the characteristics of the divisor polynomial to achieve parallel-processing for multi-bit on the word-line in the same block in a simple manner. And DDB polynomial division method can execute in multiple approaches with different hardware architectures, where the DDB divider with a parallel multiplier (PM) has the lowest hardware complexity. To demonstrate the superiority of the proposed algorithm: The time efficiency of the proposed BCH codes is successfully verified in software, proposed algorithm increases the time efficiency of encoding by more than 10 times, and the decoding increased by about 10%. The hardware implementation of proposed DDB divider is presented for improving the hardware complexity, the PM-type DDB divider architecture eliminates the large memory block of the traditional lookup-table type parallel divider.

Low-power and high-speed SRAM cells for double-node-upset recovery

This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of which can self-recover from single-node and double-node upsets. LPDNUR uses a two-input C-element structure, which reduces the average power consumption because the stacked effect. Moreover, in order to reduce read access time (RAT) and write access time (WAT), the paper proposes HSDNUR, which uses a combination of NMOS and PMOS as the transistor for one-node data transmission, an approach that increases the current drive capability and reduces transmission delays. Compared to the state-of-the-art radiation-hardened SRAM design, such as QUCCE10T, QUCCE12T, We-Quatro, etc. The model results show that the average power consumption of LPDNUR is reduced by 24.59% on average, and the RAT and WAT of HSDNUR are reduced by an average of 35.71% and 24.14% respectively.

Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits

We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.

Mechanism and Equivalence of Single Event Effects Induced by 14 MeV Neutrons in High-Speed QDR SRAM

Single-bit upset (SBU) and multiple-cell upset (MCU) features of high-speed QDR-SRAM are revealed under the 14 MeV neutron irradiation. By comparing with the high-altitude real atmosphere test results directly, the equivalence of 14 MeV neutrons for atmospheric neutron-induced single event effect (SEE) evaluation is investigated. It is found that, compared with the 65 nm planar device, the SBU cross-section of 14 nm FinFET SRAM decreases to 1/58 and the proportion of MCU shows little difference, which results from the narrow channel between fin and substrate caused by shallow channel isolation in 14 nm FinFET process, and the charge sharing effect between fins is weakened. The SBU and MCU cross-sections under the 14 MeV neutron irradiation are underestimated by 22.8% and 85.7%, respectively. Besides, the probability and maximum size of MCU are both smaller than those in the real atmosphere. The MCU shape tends to be vertical, resulting from the smaller vertical spacing of sensitive volumes (about 100 nm). Further Monte-Carlo simulation shows that the total yield of secondary ions produced by atmospheric neutrons is higher than that produced by 14 MeV neutrons. Major Components of the “useful” products are p, Si, α, etc., which are the main cause of SBU events. Besides, compared with 14 MeV neutrons, atmospheric neutrons generate more kinds of secondary ions in the SV within the scope from p to W, and the diverse high-Z elements, such as W, Ta, Hf, etc., are the main cause of MCU events. Moreover, the maximum LET of secondary ions can reach 31.5 MeV·cm2/mg. The equivalence of using 14 MeV neutrons for atmospheric neutron-induced SEE evaluation is closely related to the critical charge of the device under test.

Mechanism and Equivalence of Single Event Effects Induced by 14mev Neutrons in High-Speed Qdr Sram

Mechanism and Equivalence of Single Event Effects Induced by 14mev Neutrons in High-Speed Qdr Sram

200-MHz Single-Ended 6T 1-kb SRAM With 0.2313 pJ Energy/Access Using 40-nm CMOS Logic Process

A high-speed and low energy-consuming SRAM design based on single-ended cells is demonstrated in this work. To resolve poor SNM (static noise margin) of prior single-ended memory cells, the proposed SRAM cell is equipped with a pull-up PMOS and a high-Vthn NMOS foot switch such that the cell state is not bothered by noise when the supply voltage is getting lowered. Moreover, a PFOS (Positive Feedback Op-Amp Sensing) circuit is added between bitlines ( BL̅, BL) to reduce the read delay and generate full-swing output. Last but not least, a voltage mode select (VMS) circuit is added to each column to reduce the static power of unselected cells such that idle power is drastically reduced. The reason is that the a lower voltage able to keep the state of bits is applied to those unselected cells. A 1-kb SRAM prototype based on the proposed cells with BIST (build-in self test) circuit is physically fabricated using typical 40-nm CMOS logic process. The maximum operating clock rate is 200 MHz. The energy/access and energy/bit are measured on silicon to be 0.2313 pJ, and 0.00723 pJ, respectively.

SRAM CELL 6T AND 8T PARAMETRIC STABILITY ANALYSIS

As technology advances, the need for SRAM cells that may be utilised in high-speed applications grows. SRAM cells' static noise margin (SNM) is one of the most important variables to consider when designing a memory cell, and it is the main predictor of SRAM cell speed. The static noise margin will have an impact on the read and write margins. When it comes to the SRAM Cell's stability, the SNM is very important. For high-speed SRAMs, read/write margin analysis is critical since it affects how much data can be read and written. The simulation was run using Mentor Graphics' IC Station, which utilised 350nm technology rather than 180nm technology.

Design of High-Speed Low Variation Static Noise Margin Ternary S-RAM Cells

In this article, two ternary SRAMs are proposed with a lower delay than their predecessor. Both proposed SRAMs use an improved inverter, which is a fundamental building block of SRAMs. Due to this improvement, the speed of storing/retrieving data to/from the SRAM cells increased. The first proposed ternary SRAM cell uses different terminals for read and write operations to avoid the read disturb problem. The second proposed SRAM cell does not require an additional middle voltage (0.45V) to store ternary ‘1’. The first ternary SRAM cell requires a ternary sense amplifier to detect all the ternary level voltages, whereas the second ternary SRAM cell uses a simple two-level voltage detection sense amplifier. Further to observe the robustness of the proposed SRAM cells, Monte-Carlo analysis (process variation) was conducted over average power consumption, delay, power delay product (PDP), and static noise margin (SNM) by varying the diameter of the carbon nanotube and length of the channel.

Named data networking with neural networks for intelligent image processing information systems

ABSTRACT Rapid retrieval of differentiated name data and efficient storage of information is essential in intelligent image processing information systems. In order to meet the requirements and challenges of rapid retrieval of differentiated name data and efficient storage of image information under different application scenarios of pending interest table (PIT) of named data network, a learning PIT overall scheme is proposed. This concept is known as the Learning Tree PIT (LT-PIT), which is based on a neural network framework. The index structure of LT-PIT, improves the image information storage efficiency by learning the distribution of index content in memory. The experimental results show that the comprehensive performance of LT-PIT is better than other schemes. When the number of names reaches 2 million, the index structure memory consumption of LT-PIT is 253.129 MB, including 53.129 MB of on-chip memory consumption, which can be deployed on high-speed memory SRAM. This technique is applicable to intelligent image processing information systems and can be used to process big data of images in the future.

Strategic Development of Low Power High Speed SRAM Array Design

Because of the system variations of tiny functional size, enhanced adjustment functions in bits are becoming more and more vital, as technology nodes proceed to scale, primary memory encounter increased energy with output and time impacts such as crosstalk, challenges in consumption and reliability. We suggest a sustainable strategy to error correction in deeply-scale memories in order to tackle increasing failure rates owing to issues. SRAM is frequently used for high-speed memory apps like cache. The SRAM memory layout (SRAM) main parameter is power consumption. SRAM cells are power starving and bad in traditional models. The low-power cell designs for power consumption, delay write and the power retard product has been analyzed in this paper. The most recent upgrade VLSI, primarily in the volatile memory form of the SRAM set built into the PMOS & NMOS series and which is to be included in the cache segment on the CPU and in microcontrollers that are electronically energy-related, and now we have improved the SRAM Array challenges.

Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in 130 nm CMOS technology. The QUCCE 10T and 12T are about $2\times $ and $3.4\times $ the minimum critical charge of the conventional 6T, respectively. Compared with most of the considered state-of-the-art SRAM cells, both QUCCE 10T and 12T have comparable or better soft error tolerance, time performance, read static noise margins, and hold static noise margins, and besides, QUCCE 10T also has similar or lower costs in terms of area and leakage power. The QUCCE 10T is designed for high-density SRAMs at the nominal supply voltage. Furthermore, the QUCCE 12T saves more than 50% the read access time compared with most of the referential cells including the 6T, making it suitable for high speed SRAM designs, and it also has the best read margin, except for the traditional 8T, in terms of $\mu /\sigma $ ratio in the near threshold voltage region among all the other considered cells which nearly have no write failure in that region. Hence, the QUCCE 12T is a promising candidate for future highly reliable terrestrial low-voltage applications.

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM

A pMOS transistor with a switch is used for two purposes in a differential bitline: precharging and preamplifying during a read operation. These functions are realized by alternately changing the connection of the drain of the switching pMOS according to the operating mode. By using the same pMOS for precharging and preamplifying, the variability of a sense amplifier can be tracked, which can effectively reduce the bitline swing for the read operation. Moreover, because of the lowered bitline precharge level in the proposed scheme, the read stability is improved, as compared with that of the conventional scheme. Thus, a higher wordline voltage can be used to further improve the speed. Consequently, the delay and energy in the bitline are reduced by 1.85–5.88 times and 35%–70%, respectively, according to the supply voltage and number of cells per bitline, with a negligible area overhead of 0.9%.

Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs

A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches.

A Robust 10T SRAM Cell with Enhanced Read Operation

This paper presents a new 10T SRAM cell that has enhanced read speed along with good read and write stability. While the read access time of the proposed cell is 0.72x and 0.83x smaller as compared to the two most popular 10T SRAM cells at 50C; the read SNM is 1.16x and 1.05x higher compared to existing 10T cells. Though the read-write power of the proposed cell is higher with respect to the existing 10T cells; nevertheless, it consumes lower power as compared to the conventional 6T cell. Layout using 45nm technology rule shows that the proposed cell consumes 15% smaller area as compared to popular Schmitt-trigger based 10T SRAM cell. Also, the results of Monte-Carlo simulation show that the proposed cell is more robust against process variations. Therefore, the proposed 10T SRAM cell can be used where the speed and robustness are the primary requirements. General Terms High speed SRAM cell, Robust SRAM cell, Differential Read-Write SRAM cell.

Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies

Eight-transistor (8T) cells were introduced to improve variability tolerance, cell stability and low-voltage operation in high-speed SRAM caches by decoupling the read and write design requirements. Altogether, 8T-SRAM can be designed without significant area penalty over 6T-SRAM. Ionizing radiation effects are nowadays a major concern for reliability and dependability of emerging electronic SRAM devices, even for sea-level applications. In this paper we demonstrate from experimental results that the 8T-SRAM also exhibits an enhanced overall intrinsic tolerance to alpha particle radiation even though its critical charge values are smaller than conventional 6T cells. We have experimentally found that the soft error rate measured in accelerated experiments with alpha particles in SRAM devices implemented in a 65nm CMOS is 56% better for 8T cells with respect to standard 6T-cells. Even more, we show that this value can be increased up to a 200% through transistor sizing optimization.

Efficient hash tables for network applications.

Hashing has yet to be widely accepted as a component of hard real-time systems and hardware implementations, due to still existing prejudices concerning the unpredictability of space and time requirements resulting from collisions. While in theory perfect hashing can provide optimal mapping, in practice, finding a perfect hash function is too expensive, especially in the context of high-speed applications.The introduction of hashing with multiple choices, d-left hashing and probabilistic table summaries, has caused a shift towards deterministic DRAM access. However, high amounts of rare and expensive high-speed SRAM need to be traded off for predictability, which is infeasible for many applications.In this paper we show that previous suggestions suffer from the false precondition of full generality. Our approach exploits four individual degrees of freedom available in many practical applications, especially hardware and high-speed lookups. This reduces the requirement of on-chip memory up to an order of magnitude and guarantees constant lookup and update time at the cost of only minute amounts of additional hardware. Our design makes efficient hash table implementations cheaper, more predictable, and more practical.