Design of High-Speed Low Variation Static Noise Margin Ternary S-RAM Cells

Abstract

In this article, two ternary SRAMs are proposed with a lower delay than their predecessor. Both proposed SRAMs use an improved inverter, which is a fundamental building block of SRAMs. Due to this improvement, the speed of storing/retrieving data to/from the SRAM cells increased. The first proposed ternary SRAM cell uses different terminals for read and write operations to avoid the read disturb problem. The second proposed SRAM cell does not require an additional middle voltage (0.45V) to store ternary ‘1’. The first ternary SRAM cell requires a ternary sense amplifier to detect all the ternary level voltages, whereas the second ternary SRAM cell uses a simple two-level voltage detection sense amplifier. Further to observe the robustness of the proposed SRAM cells, Monte-Carlo analysis (process variation) was conducted over average power consumption, delay, power delay product (PDP), and static noise margin (SNM) by varying the diameter of the carbon nanotube and length of the channel.