High-speed Memory Research Articles

A High Scalability Memory NoC with Shared-Inside Hierarchical-Groupings for Triplet-Based Many-Core Architecture

Innovative processor architecture designs are shifting towards Many-Core Architectures (MCAs) to meet the future demands of high-performance computing as the limits of Moore’s Law have almost been reached. Many-core processors utilize shared memory hierarchies to achieve high-speed memory systems, improving memory access efficiency. However, as the number of cores multiplies, the scalability of this system is significantly constrained by the increased proportion of long-distance and Non-Uniform Memory Access (NUMA). Improving the scalability of MCAs is crucial for achieving large/super-scale general-purpose many-core processors. This work proposes a high scalability memory Network-on-Chip (NoC) for Triplet-Based Many-Core Architecture (TriBA), named TriBA-mNoC. TriBA-mNoC maintains a consistent core-to-core spacing as the network scale increases, effectively preventing increased long-distance memory access latency. Moreover, it leverages an inherent advantage of shared-inside hierarchical-groupings, alleviating common NUMA issues in the NoC design. Evaluations of static network characteristics show that TriBA-mNoC outperforms most classical NoCs in network diameter, average distance, and cost. TriBA-mNoC can be integrated with TriBA in the same silicon die with a tile-like floorplan, forming a novel NoC called TriBA-NoC, which can combine the strengths of both networks to maximize the architecture performance. We evaluated the memory access performance and scalability of TriBA-NoC using the mathematical evaluation models and actual simulations with real traffic (PARSEC 3.0 and SPLASH-2) at different network scales. The mathematical evaluation results indicate that TriBA-NoC achieves an aggregate speedup of approximately 3x compared with 2D-Mesh for a similar number of cores. Furthermore, TriBA-NoC’s single-core speedup efficiency remains stable as the number of cores increases under the same cache hit ratio, while 2D-Mesh experiences a rapid decline, highlighting TriBA-NoC’s exceptional scalability. Finally, the actual traffic simulation results show that TriBA-NoC achieves an average memory access latency and time reduction of 25.90% − 40.50% and 5.61% − 31.69% respectively, compared with 2D-Mesh.

Switching of ferrotoroidal domains via an intermediate mixed state in the multiferroic Y-type hexaferrite Ba0.5Sr1.5Mg2Fe12O22

We report a detailed study of the magnetic field switching of ferrotoroidal/multiferroic domains in the Y-type hexaferrite compound Ba0.5Sr1.5Mg2Fe12O22. By combining data from superconducting quantum interference device (SQUID) magnetometry, magnetocurrent measurements, and resonant x-ray scattering experiments, we arrive at a complete description of the deterministic switching, which involves the formation of a temperature-dependent mixed state in low magnetic fields. This mechanism is likely to be shared by other members of the hexaferrite family, and presents a challenge for the development of high-speed read-write memory devices based on these materials. Published by the American Physical Society 2024

Schottky barrier memory based on heterojunction bandgap engineering for high-density and low-power retention

Dynamic random-access memory (DRAM) has been scaled down to meet high-density, high-speed, and low-power memory requirements. However, conventional DRAM has limitations in achieving memory reliability, especially sufficient capacitance to distinguish memory states. While there have been attempts to enhance capacitor technology, these solutions increase manufacturing cost and complexity. Additionally, Silicon-based capacitorless memories have been reported, but they still suffer from serious difficulties regarding reliability and power consumption. Here, we propose a novel Schottky barrier memory (SBRAM), which is free of the complex capacitor structure and features a heterojunction based on bandgap engineering. SBRAM can be configured as vertical cross-point arrays, which enables high-density integration with a 4F2 footprint. In particular, the Schottky junction significantly reduces the reverse leakage current, preventing sneak current paths that cause leakage currents and readout errors during array operation. Moreover, the heterojunction physically divides the storage region into two regions, resulting in three distinct resistive states and inducing a gradual current slope to ensure sufficient holding margin. These states are determined by the holding voltage (Vhold) applied to the programmed device. When the Vhold is 1.1 V, the programmed state can be maintained with an exceptionally low current of 35.7 fA without a refresh operation.

QM-ARC: QoS-aware Multi-tier Adaptive Cache Replacement Strategy

Distributed data-centric systems, such as Named Data Networking, utilize in-network caching to reduce application latency by buffering relevant data in high-speed memory. However, the significant increase in data traffic makes expanding memory capacity prohibitively expensive. To address this challenge, integrating technologies like non-volatile memory and high-speed solid-state drives with dynamic random-access memory can form a cost-effective multi-tier cache system. Additionally, most existing caching policies focus on categorizing data based on recency and frequency, overlooking the varying Quality-of-Service (QoS) requirements of applications and customers—a concept supported by Service Level Agreements in various service delivery models, particularly in Cloud computing. One of the most prominent algorithms in caching policy literature is the Adaptive Replacement Cache (ARC), that uses recency and frequency lists but does not account for QoS. In this paper, we propose a QoS-aware Multi-tier Adaptive Replacement Cache (QM-ARC) policy. QM-ARC extends ARC by incorporating QoS-based priorities between data applications and customers using a penalty concept borrowed from service-level management practices. QM-ARC is generic, applicable to any number of cache tiers, and can accommodate various penalty functions. Furthermore, we introduce a complementary feature for QM-ARC that employs Q-learning to dynamically adjust the sizes of the two ARC lists. Our solution, evaluated using both synthetic and real-world traces, demonstrates significant improvements in QoS compared to state-of-the-art methods by better considering priority levels. Results show that QM-ARC reduces penalties by up to 45% and increases the hit rate for high priority data by up to 84%, without negatively impacting the overall hit rate, which also increases by up to 61%.

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces

Energy-efficient picosecond spin-orbit torque magnetization switching in ferro- and ferrimagnetic films.

Electrical current pulses can be used to manipulate magnetization efficiently via spin-orbit torques. Pulse durations as short as a few picoseconds have been used to switch the magnetization of ferromagnetic films, reaching the terahertz regime. However, little is known about the reversal mechanisms and energy requirements in the ultrafast switching regime. In this work we quantify the energy cost for magnetization reversal over seven orders of magnitude in pulse duration, in both ferromagnetic and ferrimagnetic samples, bridging quasi-static spintronics and femtomagnetism. To this end, we develop a method to stretch picosecond pulses generated by a photoconductive switch by an order of magnitude. Thereby we can create current pulses from picoseconds to durations approaching the pulse width available with commercial instruments. We show that the energy cost for spin-orbit torque switching decreases by more than an order of magnitude in all samples when the pulse duration enters the picosecond range. We project an energy cost of 9 fJ for a 100 × 100 nm2 ferrimagnetic device. Micromagnetic and macrospin simulations unveil a transition from a non-coherent to a coherent magnetization reversal with a strong modification of the magnetization dynamical trajectories as pulse duration is reduced. Our results show the potential for high-speed magnetic spin-orbit torque memories and highlight alternative magnetization reversal pathways at fast timescales.

Detection research of insulating gloves wearing status based on improved YOLOv8s algorithm

The safety hazards may be caused by power grid operators not wearing insulating gloves according to regulations for live electrical working. Additionally, existing methods for detecting the wearing status of insulating gloves suffer from low recognition accuracy, slow detection speed, and large memory occupation by weight files. To address these issues, a Mixup-CA-Small-YOLOv8s (MCS-YOLOv8s) algorithm is proposed for detecting the wearing status of insulating gloves. Firstly, the mixup data augmentation technology using image mixing is introduced, increasing the data’s diversity and improving the model’s generalization ability. Secondly, the coordinate attention (CA) module is added to the original backbone network to strengthen the channel and positional information, suppressing the secondary feature information. Finally, a small target detection structure is designed by removing the last bottom feature detection layer in the original neck network and adding a shallow feature. The ability of small targets’ feature extraction is enhanced without increasing too much computation. The experimental results indicate that the mean average precision of the MCS-YOLOv8s algorithm on the test set is 0.912, the detection speed is 87 FPS, and the model’s weight memory occupies 15.7 MB. It is verified that the model has the advantages of high detection accuracy, fast speed, and small weight memory, which has great significance in ensuring the safe and stable operation of the power grid.

Comparison of Current Induced Domain Wall Motion Driven by Spin Transfer Torque and by Spin Orbit Torque in Ferrimagnetic GdFeCo Wires

Current-induced domain wall motion (CIDWM) in magnetic wires can be driven by spin transfer torque (STT) originating from transferring angular momentums of spin-polarized conducting electrons to the magnetic DW and can be driven by spin orbit torque (SOT) originating from the spin Hall effect (SHE) in a heavy metal layer and Dzyaloshinsky Moriya (DMI) generated at an interface between a heavy metal layer and a magnetic layer. In this work, we carried out a comparative study of CIDWM driven by STT and by SOT in ferrimagnetic GdFeCo wires with magnetic perpendicular anisotropy based on structures of SiN (10 nm)/GdFeCo (8 nm)/SiN (10 nm) and Pt (5 nm)/GdFeCo (8 nm)/SiN (10 nm). We found that CIDWM driven by SOT exhibited a much lower critical current density (JC), and much higher DW mobility (µDW). Our work might be useful for the realization and the development of low-power and high-speed memory devices.

A versatile method for exploring the magnetooptical properties of polar saturated and unsaturated ferromagnetic metallic thin films

Polar unsaturated ferromagnetic thin films are promising for low-power and high-speed nonvolatile resistive and optical memories. Here we measure the magnetooptical (MO) response of polar unsaturated Co90Fe10 and Co40Fe40B20 thin films in the spectral range from 400 nm to 1000 nm using vector MO generalized ellipsometry (VMOGE) in an out-of-plane applied magnetic field of ±0.4 T where magnetization of the ferromagnetic (FM) thin film is not saturated. Using magnetooptical simulation software (MagOpS®), we extract the complex MO coupling constant ( Q ) of the polar unsaturated FM thin films from difference spectra of VMOGE data recorded in a polar configuration at Hz = +0.4 T and Hz = −0.4 T. The presented approach opens a path to determine Q of both polar saturated and polar unsaturated FM thin films for simulating the MO properties of application-relevant optical memory multilayer structures.

Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

In this work, a ferroelectric L-shaped tunnel FET (FE-LSTFET) is introduced to offer improvement in various DC and analog/high-frequency parameters. In this design, the incorporated FE layer enhances the vertical electric field at the source-channel interface, which improves the tunneling rate of charge carriers during the ON-state. The effect of negative capacitance (NC) and L-shaped N+ pocket causes dominance of vertical tunneling over corner tunneling (mainly at low gate voltages), which in turn reduces the transition voltage and current from 0.85 to 0.25 V and 1.2 × 10-8 to 5.67 × 10-11 A/µm respectively, thereby improving parameters such as ION, IOFF, and SSavg. Further, optimization of the thickness and doping concentration helps to keep the N+ pocket in fully depleted mode and consequently, ION/IOFF is increased from 0.3 × 1012 to 1.2 × 1014 and SSavg is reduced from 52 to 30 mV/decade. Subsequently, NC parameters such as remanent polarization (Pr) and coercive electric field (Ec) are optimized to increase the memory window, which further improves the read margin of FE-LSTFET as a memory device. Furthermore, TCAD-based simulation results show that optimizing the FE thickness improves ION and IOFF in the order of ∼ 1 and ∼ 2, respectively compared to those of C-LSTFET. With an optimum drain-overlap length, IOFF is shown to reduce from 6.6 × 10-17 to 5.43 × 10-19 A/µm due to a reduction in the SRH generation rate of the charge carriers. Despite the degradation in Cgg due to drain-overlap by the stack of FE and SiO2 layers, a significant increase in e-BTBT helps in achieving a transconductance of 2.48 × 10-4 S/µm, thus leading to a large cut-off frequency of 34.12 GHz. Next, analysis of the FE-LSTFET-based inverter shows significant improvements in several parameters including propagation delay and full swing. Moreover, FE-LSTFET shows more reluctance to self-heating effects than C-LSTFET as ION/IOFF is increased by an order of ∼ 3 at 500 K. Lastly, the performance of FE-LSTFET is benchmarked with existing TFET designs indicating that FE-LSTFET is suitable as a high-speed and low-power memory device.

Monolayer Vacancy-Induced MXene Memory for Write-Verify-Free Programming.

The fundamental logic states of 1 and 0 in Complementary Metal-Oxide-Semiconductor (CMOS) are essential for modern high-speed non-volatile solid-state memories. However, the accumulated storage signal in conventional physical components often leads to data distortion after multiple write operations. This necessitates a write-verify operation to ensure proper values within the 0/1 threshold ranges. In this work, a non-gradual switching memory with two distinct stable resistance levels is introduced, enabled by the asymmetric vertical structure of monolayer vacancy-induced oxidized Ti3C2Tx MXene for efficient carrier trapping and releasing. This non-cumulative resistance effect allows non-volatile memories to attain valid 0/1 logic levels through direct reprogramming, eliminating the need for a write-verify operation. The device exhibits superior performance characteristics, including short write/erase times (100ns), a large switching ratio (≈3×104), long cyclic endurance (>104 cycles), extended retention (>4×106s), and highly resistive stability (>104 continuous write operations). These findings present promising avenues for next-generation resistive memories, offering faster programming speed, exceptional write performance, and streamlined algorithms.

Nonvolatile memory operations using intersubband transitions in GaN/AlN resonant tunneling diodes grown on Si(111) substrates

Nonvolatile memory using intersubband transitions and quantum-well electron accumulation in GaN/AlN resonant tunneling diodes (RTDs) is a promising candidate for high-speed nonvolatile memory operating on a picosecond timescale. This memory has been fabricated on sapphire(0001) substrates to date because of the high affinity between the nitride materials and the substrate. However, the fabrication of this memory on Si(111) substrates is attractive to realize hybrid integration with Si devices and nonvolatile memory and three-dimensional integration such as chip-on-wafer and wafer-on-wafer. In this study, GaN/AlN RTDs are fabricated on a Si(111) substrate using metal-organic vapor phase epitaxy. The large strain caused by the differences in the thermal expansion coefficients and lattice constants between the Si(111) substrate and nitride materials are suppressed by a growth technique based on the insertion of low-temperature-grown AlGaN and thin AlN layers. The GaN/AlN RTDs fabricated on Si(111) substrates show clear GaN/AlN heterointerfaces and a high ON/OFF ratio of >220, which are equivalent to those for devices fabricated on sapphire(0001) substrates. However, the nonvolatile memory characteristics fluctuate by repeated write/erase memory operations. Evaluation of the ON/OFF switching time and endurance characteristics indicates that the instability of the nonvolatile memory characteristics is caused by electron leakage through deep levels in the quantum-well structure. Possible methods for suppressing this are discussed with an aim of realizing high-speed and high-endurance nonvolatile memory.

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

DDT: A Reinforcement Learning Approach to Dynamic Flow Timeout Assignment in Software Defined Networks

OpenFlow-compliant commodity switches face challenges in efficiently managing flow rules due to the limited capacity of expensive high-speed memories used to store them. The accumulation of inactive flows can disrupt ongoing communication, necessitating an optimized approach to flow rule timeouts. This paper proposes Delayed Dynamic Timeout (DDT), a Reinforcement Learning-based approach to dynamically adjust flow rule timeouts and enhance the utilization of a switch’s flow table(s) for improved efficiency. Despite the dynamic nature of network traffic, our DDT algorithm leverages advancements in Reinforcement Learning algorithms to adapt and achieve flow-specific optimization objectives. The evaluation results demonstrate that DDT outperforms static timeout values in terms of both flow rule match rate and flow rule activity. By continuously adapting to changing network conditions, DDT showcases the potential of Reinforcement Learning algorithms to effectively optimize flow rule management. This research contributes to the advancement of flow rule optimization techniques and highlights the feasibility of applying Reinforcement Learning in the context of SDN.

Fault tolerant micro-programmed control unit for SEU and MBU mitigation in space based digital systems

The Micro-Programmed Control Unit (MPCU) offers an alternative to conventional hardwired control circuits by employing a control store for transmitting control signals through stored control bits. Traditionally, Hamming codes are used for Single-Event Upset (SEU) protection in memory components. However, these Error Control Codes (ECC) encounter challenges, such as inconsistent code rates and limited adaptability for Multiple Bit Upsets (MBU). To address MBU protection, ECC codes with soft decoding logic are commonly utilized, leading to increased hardware complexity. This paper introduces a lightweight encoding and hard-decoding logic capable of detecting and correcting up to n2∗ upsets, achieving a code rate of ≈ 0.37. Through evaluations against both traditional and recent ECC methods, the proposed approach demonstrates enhanced fault correction capabilities compared to Hamming codes. Furthermore, it maintains a consistent code rate, incurs lower area overhead, and exhibits less hardware complexity than MBU codes by employing hard decoding logic. The suggested methodology effectively mitigates both MBU and SEUs in control stores, providing reduced delay and making it well-suited for ensuring reliability in high-speed memory applications like MPCUs.

2D Ferroic Materials for Nonvolatile Memory Applications.

The emerging nonvolatile memory technologies based on ferroic materials are promising for producing high-speed, low-power, and high-density memory in the field ofintegrated circuits. Long-range ferroic orders observed in 2D materials have triggered extensive research interest in 2D magnets, 2D ferroelectrics, 2D multiferroics, and their device applications. Devices based on 2D ferroic materials and heterostructures with an atomically smooth interface and ultrathin thickness have exhibited impressive properties and significant potential for developing advanced nonvolatile memory. In this context, a systematic review of emergent 2D ferroic materials is conducted here, emphasizing their recent research on nonvolatile memory applications, with a view to proposing brighter prospects for 2D magnetic materials, 2D ferroelectric materials, 2D multiferroic materials, and their relevant devices.

High-speed and energy-efficient non-volatile silicon photonic memory based on heterogeneously integrated memresonator.

Recently, interest in programmable photonics integrated circuits has grown as a potential hardware framework for deep neural networks, quantum computing, and field programmable arrays (FPGAs). However, these circuits are constrained by the limited tuning speed and large power consumption of the phase shifters used. In this paper, we introduce the memresonator, a metal-oxide memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter. These devices are capable of retention times of 12 hours, switching voltages lower than 5 V, and an endurance of 1000 switching cycles. Also, these memresonators have been switched using 300 ps long voltage pulses with a record low switching energy of 0.15 pJ. Furthermore, these memresonators are fabricated on a heterogeneous III-V-on-Si platform capable of integrating a rich family of active and passive optoelectronic devices directly on-chip to enable in-memory photonic computing and further advance the scalability of integrated photonic processors.

HfO2-ZrO2 Ferroelectric Capacitors with Superlattice Structure: Improving Fatigue Stability, Fatigue Recovery, and Switching Speed.

HfO2-ZrO2 ferroelectric films have recently gained considerable attention from integrated circuit researchers due to their excellent ferroelectric properties over a wide doping range and low deposition temperature. In this work, different HfO2-ZrO2 superlattice (SL) FE films with varying periodicity of HfO2 (5 cycles)-ZrO2 (5 cycles) (SL5), HfO2 (10 cycles)-ZrO2 (10 cycles) (SL10), and HfO2 (15 cycles)-ZrO2 (15 cycles) (SL15) were studied systematically. The HfZrOx (HZO) alloy was used as a comparison device. The SL5 film demonstrated improved ferroelectric properties compared to the HZO film, with the 2 times remnant polarization (2Pr) values increasing from 41.4 to 48.6 μC/cm2 at an applied voltage of 3 V/10 kHz. Furthermore, the first-order reversal curve diagrams of different SL and HZO capacitors at different states (initial, wake-up, fatigue, and recovery) were measured. The SL capacitors were found to effectively suppress the diffusion of defects during P-V cycling, resulting in improved fatigue stability characteristics and fatigue recovery capability compared to the HZO capacitor. Moreover, an improved switching speed of the SL films compared to the HZO capacitor was concluded based on the inhomogeneous field mechanism (IFM) model. These results indicate that the SL structure has a high potential in future high-speed ferroelectric memory applications with excellent stability and recovery capability.

Algorithm for capacity estimation based on time resolution theory with linear computational complexity for frequency-selective communication channels and PAM-n-signals

Problem statement. At that moment, it is relevant to create algorithms for communication channels capacity estimation within the framework of the Theory of Resolution Time for broadband wired telecommunication systems, which use bipolar PAM-n-signal whose execution time complexity is linear. The creation of such algorithms is of high importance both for wired network technologies (Ethernet, InfiniBand etc), and in the field of creating high-speed interchip connections, high-speed memory controllers and peripheral computer buses, since it will allow to improve channel capacity at low computational costs in real-time regime due to the transition to the “above Nyquist speed” regime. Target. Develop an algorithm which has linear computational complexity in the framework of The Resolution Time Theory for frequency-selective communication channels capacity estimation with a linear receiver and PAM-n-signal. Results. An algorithm for estimating specific channel capacity and resolution time is presented, which has linear computational complexity, depending only on the value of the effective memory, for continuous frequency-selective communication channels with a discrete source, in which information is transmitted utilizing bipolar PAM-n-signal. This algorithm has no restrictions on the pulse shape, and the computational complexity linearly depends on the channel memory. The key features of the algorithm are considered, allowing its application in real time. The developed algorithm allows to user fully estimate all the effects caused by data depended jitter. Practical significance. The proposed algorithm makes it possible in real time to select the shape of a partial pulse and the configuration of the signal constellation that increase the specific capacity of a communication system with serial data transmission, including under conditions of transmission in the “Faster than Nyquist” regime.

Design of low power SRAM cells with increased read and write performance using Read - Write assist technique

The demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes. Process, voltage, and temperature fluctuation significantly influence several performance characteristics, making it a crucial concern in nanometer SRAM design. This study presents two novel SRAM designs that effectively decrease power consumption during read operations without compromising performance or stability. A 14T SRAM has been built with an architecture that enables single-ended write and differential read operations. In addition, a 13T SRAM has been developed using an architecture that incorporates a differential write and single-ended read operation with the assistance of a write-read circuit. The two suggested SRAM cells have been fabricated using the CMOS 45 nm technology. The provided study examines the impact of modifications in process parameters on several design metrics, including the proposed cell's read-write power and current. These metrics are then compared with those of a previously suggested SRAM cell. The read power consumption of the 14T SRAM cell is reduced by 20 %, 60.63 %, 34.73 % 53.68 %, when compared to CS6T, SS8T, SS10T, and SEW10T. For the proposed 13T SRAM, the read power consumption is reduced by 147.40 %, 230.43 %, 178.2 % 217.39 %, 30.4 % when compared to CS6T, SS8T,SS10T, SEW10T, SER11T. Also the proposed SRAM II has 106.52 % lower read power when compared with proposed 14T SRAM. Also the write power of the proposed 13T SRAM is at lower side when compared to others but at the sametime write power of proposed 14T suffers from higher power consumption. Therefore the proposed 13T SRAM has been considered for the further evaluation. The RSNM and WSNM show atleast 5 % improvement when compared to existing architectures.