High-speed Low-power CMOS Research Articles

An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

Abstract: Technological innovations in the current century period have motivated professionals to make electronic gadgets smarter. These advancements are progressing at a brisk pace, facilitating faster changes and increase in computing power. Various technologies such as virtual reality, augmented reality, mobile internet, artificial intelligence, cloud computing, biometric devices, 3D printing machines, genomics, quantum computing, block-chain, industrial automation and robotics. In all these technologies, communications with nearby devices play a major role in its effective functioning. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power CMOS receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 180nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.8V, a clock frequency of 50MHz

Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth) or for low power dissipation (high-Vth). The latch stage of the proposed DTDC is designed with novel dynamic CMOS inverters to improve the regeneration speed. The mathematical equations for delay and offset voltage are derived for the proposed DTDC and improvements are mentioned. The proposed DTDC is designed in CADENCE and simulated with SPECTRE using 45 nm CMOS process technology at the low power supply of 0.8 V to verify the outcomes. The simulation results reveal that the delay and power dissipation of the proposed DTDC are 166.29 pS and 2.3 µW respectively. The analysis of 1-sigma offset error is performed using Monte-Carlo simulation. Here, the mismatch and process variation are considered and the samples are generated randomly till 200 samples (runs). Additionally, the peak input voltage error due to kickback noise is 0.219 mV for a differential input voltage of 5 mV.

A High-speed Low-power CMOS Image Sensor with Delta and Interpolation Readout Scheme

A High-speed Low-power CMOS Image Sensor with Delta and Interpolation Readout Scheme

88-<formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for<newline/> Differential Capacitive Sensors

The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance. Therefore, the main limitation of all previous current-mode techniques is nearly eliminated. Besides, as an additional distinctive aspect, the proposed solution is suitable for both linear- and hyperbolic-type capacitive sensors. To validate the idea an interface circuit was designed in a 65-nm CMOS technology powered from a 2.5-V supply and dissipating 88- μA standby current. Measurements show that relative capacitive sensor variations up to ± 900 fF ( ± 100% of the nominal value) even in presence of a large parasitic capacitance of 2.5 pF are detected in less than 1 μs with a sensitivity of about 5 nA/fF and with an relative error lower than ± 1.5%, without requiring digital calibration.

(Invited) The Materials Integration of Ge and InxGa1-X As on Si Template for Next Generation CMOS Applications

Lately, the semiconductor industry has paid a lot of attentions to the III-V compound semiconductor materials such as InSb, InxGa1-xAs for next generation CMOS applications, because these materials have significantly higher carrier mobility than silicon. For example, the electron mobility of InAs could reach 20000 cm2V-1s-1. High-speed devices such as quantum-well field-effect transistors (QWFETs) made from these III-V materials have demonstrated very low gate delay time. However, hole mobility for III-V materials are very low in general, some are even lower than the hole mobility of Si. So, it is important to look for a proper material with high hole mobility as p-channel FETs for future complementary CMOS architecture. Since Ge has a much higher bulk hole mobility (mh =1900 cm2/Vs) as compared to GaAs (mh = 400 cm2/Vs), Ge is suitable as p type channel material. Due to the small lattice mismatch (~0.08%) between GaAs and Ge, the integration of Ge with GaAs is comparable easy as compared to grow on Si , therefore thick Ge film can be grown as channel on GaAs substrates with very low defect density and integrate with InxGa1-xAs devices as a CMOS structure. In this talk, the growth of high quality Ge film on GaAs substrate by ultra high vacuum chemical vapor deposition (UHVCVD) and high quality InAs material on Ge/SiGe/Si template grown by molecular beam epitaxy (MBE) will be particularly reported. By the observation of XRD and AFM, both Ge film grown on GaAs material and InAs grown on Si substrates demonstrate high crystallinity and good surface morphology. The developed epitaxial materials systems including Ge on GaAs and InAs on Si are useful for future III-V/Ge/Si integration for next generation high speed low power CMOS application as well as for RF/digital mixed signal circuit application in the future.

A High Speed-Low Power Comparator with Composite Cascode Pre-amplification for Oversampled ADCs

This paper presents a high speedlow power CMOS comparator using composite cascode differential pair as a pre-amplification stage. The purpose of this work is to design a comparator for oversampled ADC application. This comparator is designed using 180nm CMOS technology with a power supply of 1.2V. Pre and post layout simulation of the proposed circuit is done using cadence tool. The total power consumption of the comparator is 71.61μW and unity gain-bandwidth is 1GHz. The DC offset voltage is 12mV, gain is 70dB while total area occupied by comparator is 684μm 2 . This design achieves an OSR (Oversampling Sampling Ratio) greater than 1000 which corresponds to SNR improvement of 30dB for Σ-Δ converters. 

Reduced comparator high speed low power ADC using 90 nm CMOS technology

The increasing demand of high speed and low power ADC in serial links, gigabit ethernet, high speed instruments in general and communication technologies such as ultra wide band systems in particular has put tremendous pressure on efficient design of data converters. Presently flash ADC is the architecture of choice with sampling frequency ranging from 2 to 40 GS/s with 4---6 bit resolution, where speed and low resolution is required. However we are forced to compromise between performance and complexity when such ADC is used. In this paper a single channel high speed low power CMOS based 4-bit ADC using reduced comparator and multiplexer based architecture is presented. For improving the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the proposed ADC are fully modified and the architecture uses only 4 comparators instead of 15 as used in conventional flash ADC, thereby saving considerable amount of power. The proposed 4-bit 2 GS/s ADC is designed and simulated in Tanner tools with 1.2 V supply voltage using 90 nm CMOS technology. HSpice simulation result of proposed architecture shows a power dissipation of 23 mW with INL and DNL errors between ±0.4 LSB and ±0.34 LSB respectively. ENOB and SNDR for the proposed architecture are 3.72 and 24.2 respectively.

The Integration of Ge and III-V Materials on GaAs and Si for Post CMOS Applications

In the study, the growth of InAs on Si is demonstrated using "interface blocking" technique with SiGe layers as buffer layer. And the growth of high quality Ge film on GaAs is demonstrated using ultra high vacuum chemical vapor deposition (UHVCVD). Both Ge film grown on GaAs and InAs film grown on Si substrate demonstrate high crystallinity and good surface morphology as observed by XRD and AFM. Furthermore, the fabrication process and electric characteristics of Ge/GaAs and InAs/Si is discussed in the study. The developed epitaxial materials systems and device fabrication including InAs on Si, Ge on GaAs are useful for future III-V and Ge integration on Si substrate for next generation high speed low power CMOS as well as for RF/digital mixed signal circuit applications in the future.

High-speed low-power CMOS comparator dedicated to 10 bit 20 MHz pipeline ADCs for RF WLAN applications

This article describes and analyses a low power and high speed comparator. The designed comparator is intended to be implemented in a 10 bit 20 MHz Pipeline Analogue-to-Digital Converter dedicated to RF Wireless Local Area Network (WLAN) applications. This comparator is based on the switched capacitor network using a two-phase non-overlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8 µm CMOS AMS process parameters, with a power supply voltage of 5 V and an input common mode of 2–3 V, show that this comparator exhibits a propagation delay of 17.3 ns, an offset voltage of about 77.3 mV, a good accuracy and a low power consumption of about 0.8 mW. The predicted performance is verified by analyses and simulations using PSPICE tool.

Low power high-speed CMOS dual-modulus prescaler design with imbalanced phase-switching technique

A novel imbalanced phase-switching technique for high-speed prescaler design is investigated. Different from the traditional 50% duty cycle phase-switching technique, it uses 1/4 duty cycle phases to increase the delay budget in dual-modulus control. It significantly improves the performance of the prescaler in terms of operating frequency and power consumption, compared with the existing 50% duty cycle phase switching technique. This improvement makes it applicable to ultra-high-speed CMOS prescaler design. Two prescalers, with 2-to-1 and 4-to-1 phase switching are designed using this technique. The proposed 2-to-1 phase switching divide-by-7/8 prescaler with simplified topology using the Chartered 0.18 micron CMOS process is capable of operating from 1.5 GHz to 6 GHz with a 7 mW power consumption from a 1.8 V supply. Such operating frequency ranges cover most of the wireless LAN standards. The prescaler with 4-to-1 phase switching can work from 2 GHz to 10 GHz with a power consumption of 15 mW from a 1.8 V supply. The proposed technique is promising in relation to multi-GHz CMOS prescaler design because it eliminates the design trade-offs associated with other techniques.

A design for high-speed low-power CMOS fully parallel content-addressable memory macros

Described is a design for high-speed low-power-consumption fully parallel content-addressable memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-/spl mu/m 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256/spl times/54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions.

A variable-frequency parallel I/O interface with adaptive power-supply regulation

This paper presents a low-power high-speed CMOS signaling interface that operates off of an adaptively regulated supply. A feedback loop adjusts the supply voltage on a chain of inverters until the delay through the chain is equal to half of the input period. This voltage is then distributed to the I/O subsystem through an efficient switching power-supply regulator. Dynamically scaling the supply with respect to frequency leads to a simple and robust design consisting mostly of digital CMOS gates, while enabling maximum energy efficiency. The interface utilizes high-impedance drivers for operation across a wide range of voltages and frequencies, a dual-loop delay-locked loop for accurate timing recovery, and an input receiver whose bandwidth tracks with the I/O frequency to filter out high-frequency noise. Test chips fabricated in a 0.35-/spl mu/m CMOS technology achieve transfer rates of 0.2-1.0 Gb/s/pin with a regulated supply ranging from 1.3-3.2 V.

The charge-transfer feedback-controlled split-path CMOS buffer

A new low-power high-speed CMOS buffer, called the charge-transfer feedback-controlled split-path (CFS) CMOS buffer, is proposed. By using the feedback-controlled split-path method, the short circuit current of the output inverter is eliminated. Four additional MOS transistors are used as the charge-transfer diodes, which can transfer the charge stored in the split output-stage driver to the output node. Thus the propagation delay and power dissipation of the CFS buffer are reduced. The HSPICE simulation results show that the power-delay product of the CFS CMOS buffer is a savings over 20% in comparison to a conventional CMOS tapper buffer at 100 MHz operation frequency.

Low-power circuit design techniques for multimedia CMOS VLSIs

Power dissipation of CMOS integrated circuits continues to increase as a result of device scaling. In this paper circuit design techniques for high-speed low-power CMOS VLSIs for multimedia applications are reviewed. In addition to general guidelines for low-power design and a summary of recent research, we discuss in detail some of the recent research achievements including low-voltage circuits such as MTCMOS and VTCMOS, and low-capacitance circuits such as pass-transistor logic circuits. © 1998 Scripta Technica, Electron Comm Jpn Pt 3, 81(9): 67–74, 1998

Low‐power circuit design techniques for multimedia CMOS VLSIs

Power dissipation of CMOS integrated circuits continues to increase as a result of device scaling. In this paper circuit design techniques for high-speed low-power CMOS VLSIs for multimedia applications are reviewed. In addition to general guidelines for low-power design and a summary of recent research, we discuss in detail some of the recent research achievements including low-voltage circuits such as MTCMOS and VTCMOS, and low-capacitance circuits such as pass-transistor logic circuits. © 1998 Scripta Technica, Electron Comm Jpn Pt 3, 81(9): 67–74, 1998

Variable supply-voltage scheme for low-power high-speed CMOS digital design

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-/spl mu/m CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design

Lowering supply voltage,VDD, is the most effective means to reduce power dissipation of CMOS LSI design. In lowVDD, however, circuit delay increases and chip performance degrades. There are two means to maintain the chip performance: 1) to lower the threshold voltage,Vth, to recover circuit speed, or 2) to introduce parallel and/or pipeline architectures to make up for slow device speed. The first approach increases standby power dissipation due to lowVth, while the second approach degrades worst case circuit speed caused byVth fluctuation in lowVDD. This paper presents two circuit techniques to solve these problems, in both of whichVth is controlled through substrate bias. A Standby Power Reduction (SPR) scheme raisesVth in a standby mode by applying substrate bias with a voltage-switch circuit. A Self-Adjusting Threshold-Voltage (SAT) scheme reducesVth fluctuation in an active mode by adjusting substrate bias with a feed-back control circuit. Test chips are fabricated and effectiveness of the circuit techniques is examined. The SPR scheme reduces 50% of the active power dissipation while maintaining the speed and the standby power dissipation. The SAT scheme improves worst case circuit speed by a factor of 3 under a 1 VVDD.

A CMOS 8-Bit High-Speed A/D Converter IC

A novel high-speed low-power CMOS balanced comparator circuit is proposed and implemented in an 8M fully parallel analog-to-digital (A/D) converter IC. A 20-MHz sampling rate with 350-mW power dissipation from a single 5-V power supply has been realized. Integral linearity of /spl plusmn/ 1/2 LSB to 8-bit conversion has been achieved through intensive transistor dimension optimization applied to the comparator circuit, instead of employing an offset canceling technique.

A high-speed low-power Hi-CMOS 4K static RAM

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.