Reduced comparator high speed low power ADC using 90 nm CMOS technology

Abstract

The increasing demand of high speed and low power ADC in serial links, gigabit ethernet, high speed instruments in general and communication technologies such as ultra wide band systems in particular has put tremendous pressure on efficient design of data converters. Presently flash ADC is the architecture of choice with sampling frequency ranging from 2 to 40 GS/s with 4---6 bit resolution, where speed and low resolution is required. However we are forced to compromise between performance and complexity when such ADC is used. In this paper a single channel high speed low power CMOS based 4-bit ADC using reduced comparator and multiplexer based architecture is presented. For improving the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the proposed ADC are fully modified and the architecture uses only 4 comparators instead of 15 as used in conventional flash ADC, thereby saving considerable amount of power. The proposed 4-bit 2 GS/s ADC is designed and simulated in Tanner tools with 1.2 V supply voltage using 90 nm CMOS technology. HSpice simulation result of proposed architecture shows a power dissipation of 23 mW with INL and DNL errors between ±0.4 LSB and ±0.34 LSB respectively. ENOB and SNDR for the proposed architecture are 3.72 and 24.2 respectively.