High-speed low-power CMOS comparator dedicated to 10 bit 20 MHz pipeline ADCs for RF WLAN applications

Abstract

This article describes and analyses a low power and high speed comparator. The designed comparator is intended to be implemented in a 10 bit 20 MHz Pipeline Analogue-to-Digital Converter dedicated to RF Wireless Local Area Network (WLAN) applications. This comparator is based on the switched capacitor network using a two-phase non-overlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8 µm CMOS AMS process parameters, with a power supply voltage of 5 V and an input common mode of 2–3 V, show that this comparator exhibits a propagation delay of 17.3 ns, an offset voltage of about 77.3 mV, a good accuracy and a low power consumption of about 0.8 mW. The predicted performance is verified by analyses and simulations using PSPICE tool.