High-speed Frequency Divider Research Articles

A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

Injection locking at zero field in two free layer spin-valves

This paper predicts the possibility to achieve synchronization (via injection locking to a microwave current) of spin-transfer torque oscillators based on hybrid spin-valves composed by two free layers and two perpendicular polarizers at zero bias field. The locking regions are attained for microwave frequency near 0.5f0, f0, and 2f0, where f0 is the input oscillator frequency. Those properties make this system promising for applications, such as high-speed frequency dividers and multipliers, and phase-locked-loop demodulators.

Bandwidth-Related Optimization in High-Speed Frequency Dividers using SiGe Technology

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.

A dual-mode 6–9 GHz transmitter for OFDM-UWB

This paper presents a fully integrated dual-mode 6 to 9 GHz transmitter for both WiMedia and China MB-OFDM UWB applications. The proposed transmitter consists of a dual-mode I/QLPF, an up-conversion mixer, a two-stage power driver amplifier and a broadband high-speed frequency divider with LO buffers for I/Q LO carrier generation. The measurement results show that the gain ripple of the transmitter is within ±1.5/±2.8 dB from 6 to 8.7/9 GHz. The output IP3 is about +13.2 dBm, the output 1dBCP is around +2.8 dBm, and the LO leakage/sideband rejection ratio is about −35/−38 dBc. The ESD protected chip is fabricated with a TSMC 0.13 μm RFCMOS process with a die size of 1.6 × 1.3 mm2 and the core circuit consumes only 46 mA under a 1.2 V supply.

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications

This paper presents a low phase noise frequency synthesizer for WiMAX applications. The operating frequency of the proposed design ranges from 2.2GHz to 2.4GHz with a 1.25MHz spacing for the 1.25MHz to 40MHz channel bandwidth. The proposed VCO suppresses the phase noise effectively by adopting the Q-enhancement technique, the memory reduced tail current, and a noise filter. The high speed frequency divider is implemented by an improved TSPC D-flip-flop. The proposed design is fabricated in a TSMC 0.18µm CMOS 1P6M process. The measured phase noise is -118Bc/Hz at an offset of 1MHz from the center frequency. The fabricated chip consumes 25.5mW with a 1.5V supply and occupies a 1.1mm2 die area.

Frequency synthesiser architecture eliminating high speed frequency dividers for millimetre-wave applications

A frequency synthesiser architecture for millimetre-wave applications is proposed. The architecture is based on a triple-push oscillator, which functions both as a divider and oscillator. Thus, the proposed architecture eliminates the need for injection locked frequency dividers that are the main contributors to the limited tuning capability of millimetre-wave phase-locked loops. Since the proposed architecture is solely based on the performance of the triple-push oscillator, the measurement result of the first silicon triple-push oscillator at 30 GHz is presented to support the validity of the concept.

Heterodyne Phase Locking: A Technique for High-Speed Frequency Division

A phase-locked loop incorporating a cascade of mixers can provide integer or fractional divide ratios at high frequencies. The circuit topology and its variants are presented, and their advantages over static, dynamic, and injection-locked dividers are described. The effect of nonidealities such as the spurious response and noise of the mixers is also analyzed. A divide-by-two prototype realized in 0.13-mum CMOS technology operates from 64 GHz to 70 GHz while consuming 6 mW from a 1.2-V supply.

High-speed SiGe HBTs and their applications

The structure of a high-speed self-aligned SiGe heterojunction bipolar transistor (HBT) was optimized through investigations of its characteristics related to the collector-base and emitter-base junctions. The SiGe HBT was fabricated by selective-epitaxial growth (SEG). As a result of the optimization, its cutoff frequency was increased to 130 GHz and its ECL gate-delay time was reduced to 5.3 ps. Based on this SiGe HBT, an IC chipset for 40 Gb/s optical-fiber-links, a 5.8 GHz electronic-toll-collection transceiver IC, and high-speed frequency divider ICs (operating up to the millimeter-wave band) were developed.

Design of low-power high-speed bipolar frequency dividers

A low-power current mode bipolar frequency divider is discussed. Low-power consumption is achieved owing to the design strategy being based on a progressive reduction of bias currents through stages without affecting divider operation speed. The strategy is independent of the process used and simple to design, avoiding the trial-and-error approach based on simulations.

High-speed CMOS frequency divider

A high-speed CMOS frequency divider is proposed. Using fewer transistors and only NMOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and larger transconductance. A device sizing rule for the maximum input frequency is given. The proposed frequency divider is suitable for high-speed operational while consuming a moderate amount of power.

46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology

High-speed multiplexers, demultiplexers, and static frequency dividers are key electronic components in future optical broadband communication systems. In this paper we present a 50 Gb/s multiplexer, a 46 Gb/s demultiplexer, and a 30 GHz static frequency divider. The IC's were fabricated in a self-aligning double-polysilicon bipolar technology using state-of-the-art production process modules. The achieved results are record speeds not only for silicon, but, except for the static divider, for all semiconductor technologies. The high performance of this chipset shows that circuits in silicon bipolar technology will play an important role in future multigigabit-per-second fiber-optic communication systems, at data rates of 20 Gb/s or even at 40 Gb/s.

GaAs HBT's for high-speed digital integrated circuit applications

GaAs HBT technology has emerged as one of the most important developments for digital circuits operating at clock frequencies of 100 MHz and higher. High-speed frequency dividers operating as high as 34.8 GHz and VLSI circuits as complex as 32-b CPU's operating at 200-MHz clock rate have been demonstrated. This paper reviews the role of GaAs HBT technologies for high-speed digital IC applications. The requirements for high-speed IC's and the characteristics of various HBT device structures and logic families are discussed. A summary of published results of the ultrahigh-speed circuits and the status of several high-speed VLSI circuits are presented to provide a guide for future developments. >

Ultra-high speed semiconductor devices and low temperature electronics

This paper reviews recent progress in GaAs MESFETs and HBTs for high speed integrated circuits. SAINT MESFETs have succeeded in scaling down gate lengths to 0.1–0.15 μm and have realized propagation delay times of 5.9 ps gate −1. A multiplexer and demultiplexer operating at a high bit rate of 11.2 Gbit s −1 has also been developed. HBTs with ballistic collection transistor (BCT) structure have been proposed and have demonstrated highest speeds of 1.9 ps gate −1. High speed frequency dividers operating at 34.8 GHz have also been realized. Quantum interference transistors, which may provide innovations in future high performance devices, are also discussed.

A 5.1-GHz 1.9-mW GaAs binary frequency divider

A GaAs divide-by-two circuit operating at a clock rate of 5.1 GHz and dissipating only 1.9 mW has been demonstrated. This represents the best room-temperature speed-power performance yet reported for any flip-flop. The D-type flip-flop owes its high performance to a 0.5- mu m TiWN self-aligned gate fabrication process using low-capacitance dielectric material. The speed-power performance with this process is compared to other recent results for high-speed frequency dividers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

18-GHz 1/8 dynamic frequency divider using Si bipolar technologies

Circuit technology to achieve high-speed frequency dividers using Si bipolar devices is studied. A novel circuit configuration based on regenerative frequency division was proposed and analyzed. It is determined that the 3-dB-down bandwidth of the open loop of the novel circuit configuration is three times higher than that of the conventional circuit and that it operates almost up to the f/sub T/ of the transistor. A 1/8 dynamic divider using this novel circuit configuration was fabricated with advanced super self-aligned process technology (SST-1B). The divider operates between 4.6 and 18 GHz. It is noted that the circuit technology and process technology described are applicable to very-high-speed prescalers for satellite communication systems and high-speed measuring equipment.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 20-GHz frequency divider implemented with heterojunction bipolar transistors

This paper reports a high-speed frequency divider implemented with AlGaAs/InGaAs/GaAs heterojunction bipolar transistors (HBT's). The divide-by-four static frequency divider was fabricated with a fully self-aligned dual-lift-off HBT process. A maximum operating frequency of 20.1 GHz was achieved. This is the highest frequency ever reported for static frequency dividers.

A high-speed frequency divider using n+-Ge Gate AlGaAs/GaAs MISFET's

A high-speed divide-by-four static frequency divider is fabricated using n+ -Ge gate AlGaAs/GaAs heterostructure MISFET's. The divider circuit consists of two master-slave T-type flip-flops (T-FF's) and an output buffer based on source-coupled FET logic (SCFL). A maximum toggle frequency of 11.3 GHz with a power dissipation of 219 mW per T-F/F is obtained at 300 K using 1.0-µm gate FET's.

High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistors

A divide-by-four frequency divider and ring oscillators have been fabricated employing self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBT's). Maximum toggle frequency of 13.7 GHz and propagation delay time of 17.2 ps are achieved in ECL gate circuitry. These values are the highest and the lowest in ECL circuits and in bipolar circuits, respectively, ever reported.

High-speed GaAs frequency dividers using a self-aligned dual-level double lift-off substitution gate MESFET process

A new self-aligned substitution gate process, which uses a dual-level resist (photoresist/polymethylmethacrylate (PMMA)) and a double lift-off technique has been successfully developed for the fabrication of MESFET circuits on 3-in GaAs wafers. Good device uniformity (20-mV standard deviation of threshold voltage) and excellent device characteristics ( g_{m} = 280 mS/mm) were obtained. Single-clocked divide-by-four frequency dividers with direct-coupled FET logic (DCFL) and five-gate delay design were fabricated by the above process. The maximum input frequency measured was 4.4 GHz. The minimum power dissipation was a 0.55-mW/gate with a speed-power product of 39 fJ.