High-speed Frequency Divider Research Articles

High-speed frequency dividers using GaAs/GaAlAs high-electron-mobility transistors

Very-high-speed divide-by-four circuits have been fabricated by using modulation-doped GaAs/GaAlAs high-electron-mobility transistors. The circuits consist of two T-connected D-flip-flops and are capable of operating at 3.6 GHz with a power dissipation of 0.46 mW per gate at room temperature, and at 5.2 GHz with a power dissipation of 0.78 mW per gate at 77 K. The speed-power products achieved are the lowest ever reported.

High-speed frequency dividers with quasi-normally-off GaAs MESFETs

Master-slave binary frequency dividers have been designed and implemented with enhancement-mode GaAs MESFETs by using the so-called LPFL logic approach. A wide range of speed-power performances has been observed: a maximum toggle frequency of 2.8 GHz at P = 15 mW/gate on a dual-clocked frequency divider and an fc,max of 1.73 GHz at Pxtpd = 1 pJ/gate on a single-clocked one. The high-speed performance obtained corresponds to a propagation delay of 145 ps for the constituent NOR-OR gates of fan-in/fan-out = 4/3, and it is made possible by careful optimisation of circuit design parameters.

GaAs digital integrated circuits for very high-speed frequency division

Dual- and single-clocked frequency dividers, consisting of normally-on GaAs MESFET integrated circuits, with maximum toggle frequency of 5.7 GHz, were fabricated. The gate length was 0.8 μm and an E-beam direct writing processing technology was used. Some improvements, such as reduction of the gate length and adoption of a double pinchoff voltage technology, would make possible the implementation of a counter family with a maximum operating frequency in the range 5–7 GHz.

A 1 GHz Low Power 2 Modulus Frequency Divider

This paper presents a high speed frequency divider which performs 2-modulus operation with the division ratio of 128 and 136 at a. frequency range over 1 GHz.

Charge injection from a surface depletion region—the Al 2O 3-silicon system : J. Kolk and E. L. Heasell. Solid-St. Electron.23, 223 (1980)

The structure of a high-speed self-aligned SiGe heterojunction bipolar transistor (HBT) was optimized through investigations of its characteristics related to the collector-base and emitter-base junctions. The SiGe HBT was fabricated by selective-epitaxial growth (SEG). As a result of the optimization, its cutoff frequency was increased to 130 GHz and its ECL gate-delay time was reduced to 5.3 ps. Based on this SiGe HBT, an IC chipset for 40 Gb/s optical-fiber-links, a 5.8 GHz electronic-toll-collection transceiver IC, and high-speed frequency divider ICs (operating up to the millimeter-wave band) were developed.