Abstract
Master-slave binary frequency dividers have been designed and implemented with enhancement-mode GaAs MESFETs by using the so-called LPFL logic approach. A wide range of speed-power performances has been observed: a maximum toggle frequency of 2.8 GHz at P = 15 mW/gate on a dual-clocked frequency divider and an fc,max of 1.73 GHz at Pxtpd = 1 pJ/gate on a single-clocked one. The high-speed performance obtained corresponds to a propagation delay of 145 ps for the constituent NOR-OR gates of fan-in/fan-out = 4/3, and it is made possible by careful optimisation of circuit design parameters.
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