Abstract
A GaAs divide-by-two circuit operating at a clock rate of 5.1 GHz and dissipating only 1.9 mW has been demonstrated. This represents the best room-temperature speed-power performance yet reported for any flip-flop. The D-type flip-flop owes its high performance to a 0.5- mu m TiWN self-aligned gate fabrication process using low-capacitance dielectric material. The speed-power performance with this process is compared to other recent results for high-speed frequency dividers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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