Abstract
A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.
Highlights
Phase-locked loop (PLL)-type frequency synthesizers are widely used to generate local frequency signals in RF transceivers
This paper presents an improved programmable frequency divider for a Ka-band PLLtype frequency synthesizer in a 90 nm CMOS process
An improved programmable frequency divider is fabricated in a 90 nm CMOS technology
Summary
Phase-locked loop (PLL)-type frequency synthesizers are widely used to generate local frequency signals in RF transceivers. Important specifications, such as a wide operation frequency range, low phase noise, and low power consumption are significant to programmable frequency dividers [4,5,6]. A suitable, programmable frequency divider based on a dual-modulus prescaler (DMP) and pulse swallow (PS) counters with a higher operating frequency and a wider operation frequency range seems advantageous [12,13].
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