High-speed Divider Research Articles

A 4.1 GHz–9.2 GHz Programmable Frequency Divider for Ka Band PLL Frequency Synthesizer

High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.

Implementation of Quaternary Divider for Performance Optimization

In VLSI technology, designers concentrations is on area required and on performance of the device. In this design power consumption is one of the major concerns due to increase in chip density, continuous and decline in size of CMOS circuits and frequency at which circuits are operating. High-speed divider is an significant issue of high-speed computing. This paper presents quaternary division algorithm .This algorithm involves detect zero circuit designed with transmission gate. This proposed algorithm is faster than binary division algorithm as well as radix 4 SRT division algorithm in terms of speed & power. This type of fast divider can be used for the design of Arithmetic Logic unit.

A Hybrid Topology for Frequency Divider using PLL Application

In this paper, we present a new type of odd integer divider topology which consume low power and it uses Mod-N counter, DFF and OR gate. In existing methodology divide by 2 topologies involves only D Flip-Flops (DFF), which realized mostly Common Mode Logic DFF (CML) or True Single Phase Clock (TSPC) based DFF. These were high-speed dividers but no flexibility in this topology i.e. it divides the only power of N. So the proposed divider gives more flexibility to the topology like divided by any real odd integer. While designing a new topology the limitations are operating frequency range, a number of transistor and power consumption. Based on this consideration the 3T NAND and TSPC based Flip-Flop are investigated. The maximum operating frequency of the TSPC divide by 2 is reaches at 2.4 GHz with 1.1931 mw power consumption and is 50% low power consumption compared to the NAND_DFF based frequency divider. Similarly, divide by 3, divide by 5 and divide by 7 also consume low power with less number of transistor compare to the NAND_DFF based frequency divider. So the results show the TSPC is DFF’s more preferable for PLL application and RFIC. The TSPC_DFF based frequency divider designed using 0.18 um CMOS process technology.

A 6.1 mW 7.5–10.6 GHz PLL-based frequency synthesizer for IEEE 802.15.4a UWB transceivers

A low power 7.5---10.6 GHz frequency synthesizer for impulse radio ultra-wide band (IR-UWB) is designed and fabricated in 65 nm CMOS technology. The synthesizer is based on an integer-N type-II 4th-order PLL architecture. A 7-bit voltage-controlled oscillator with 31 % tuning range and a set of high-speed dividers are used to synthesize all the carriers defined by the IEEE standard 802.15.4a. The frequency dividers are based on true single phase clock logic resulting in compact implementation and low power consumption. The 0.33 mm2 fully integrated synthesizer consumes 5.13 mA from a 1.2 V supply. With a 3-dB closed-loop bandwidth of 100 kHz, the settling time is 15 µs. It features <ź103 dBc/Hz measured phase noise at 1 MHz offset. The out-of-band spurious tones result below ź59 dBc.

A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications

ever increasing demand in VLSI architecture to handle complex systems has resulted for designing of high speed divider architecture. The divider is designed using ever known ancient methodology mathematics. There are several methods present in Vedic mathematics but here Parvartya sutra is used. It is a general division formula which can be applicable to all cases of division which is an efficient way for dividing large numbers with respect to delay and power consumption. Here thirty-two bit divider architecture is implemented using this sutra & synthesized and simulated using Xilinx ISE simulator and implemented on virtex4 FPGA device XC4VLX15.The output parameters such as propagation delay and device utilization are calculated from synthesis results. Our result shows speed improvement as compared to other architecture presented in this literature. This architecture can be implemented in many applications such as digital signal processing, cryptography, processor arithmetic unit design etc.

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6dBc/Hz at 1MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1mW. The chip with an area of 1.048×1.076mm2 is fabricated in a TSMC 0.18μm CMOS 1P6M technology process.

A current-mode RF transmitter for 6–9 GHz MB-OFDM UWB application

This paper presents a current-mode 6–9 GHz RF transmitter for MB-OFDM UWB systems. The proposed current-mode transmitter consists of current-mode IQ LPF, current mirror amplifier, IQ up-conversion mixer (up-mixer), differential power driver amplifier (PA) and high-speed divider with LO buffers for generating IQ LO signals. All circuits are designed to possess high linearity and wide bandwidth. The transmitter is fabricated in TSMC 0.13 μm 1P8M RF CMOS technology with a die area of 1.56 mm2. Measurement results show that a maximum output power of −0.7 dBm with an LO leakage/sideband rejection ratio (LOL/SB RR) around −33/ −35 dBc is achieved, and that this transmitter excels the traditional voltage-mode counterpart in terms of high linearity (about +1 dBm output 1-dB compression point, +10 dBm output IP3 in average) with comparable power consumption (drawing 48 mA current from 1.2 V supply).

An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications

We present an integrated frequency synthesizer which is able to provide in-phase/quadrature phase signal over the frequency bands 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and in-phase signal over 20-28 GHz for software-defined radio applications. An integrated voltage-controlled oscillator (VCO) with 34% tuning range and a set of high-speed dividers are used to accomplish all the frequencies. To achieve a wide tuning range while keeping a low gain and a low phase noise, the VCO employs digitally controlled sub-bands. The measured PLL phase noise is - 108 dBc/Hz, -121 dBc/Hz, and -135 dBc/Hz at 1 MHz offset for 24 GHz, 4 GHz, and 700 MHz, respectively. Fabricated in a 0.25 μm SiGe BiCMOS process, the synthesizer occupies a chip area of 4.8 mm2. The synthesizer was optimized for reconfigurable base station applications, but can also be used for cognitive radio, radar systems, satellite communication, and high-speed digital clock generation.

Design and VLSI evaluation of a high-speed cellular array divider with a selection function

In recent years, very fast dividers have been required for the real-time application of digital signal processing, robot control, and the like. This paper proposes a high-speed cellular array divider with a selection function that is based on the non-restoring algorithm and can deal with both fixed-point and negative operands in two's complement form. This divider uses new techniques that can generate in parallel both the quotient bit of one row and a partial remainder and CLS bit of the next row. The delay time of the proposed divider is calculated in terms of a delay of one unit such as a NAND gate. Finally, by using PARTHENON, a CAD (computer-aided design) system for VLSI, this divider is designed and evaluated. As a result, elimination of the delay time for even rows becomes possible. Thus, the delay time can be decreased to approximately one half that of the high-speed divider proposed by Cappa and Hamacher, which uses the most general high-speed techniques of carry-save and CLA.

A Numerically Approximate High-speed Divider for Image Processing Applications

A Numerically Approximate High-speed Divider for Image Processing Applications

A 4-GHz clock system for a high-performance system-on-a-chip design

A digital system's clocks must have not only low jitter, but also well-controlled duty cycles in order to facilitate versatile clocking techniques. Power-supply noise is often the most common and dominant source of jitter on a phase-locked loop's (PLL) output clock. Jitter can be minimized by regulating the supply to the PLL's noise-sensitive analog circuit blocks in order to filter out supply noise. This paper introduces a PLL-based clock generator intended for use in a high-speed highly integrated system-on-a-chip design. The generator produces clocks with accurate duty cycles and phase relationships by means of a high-speed divider design. The PLL also achieves a power-supply rejection ratio (PSRR) greater than 40 dB while operating at frequencies exceeding 4 GHz. The high level of noise rejection exceeds that of earlier designs by using a combination of both passive and active filtering of the PLL's analog supply voltage. The PLL system has been integrated in a 0.15-/spl mu/m single-poly 5-metal digital CMOS technology. The measured performance indicates that at a 4-GHz output frequency the circuit achieves a PSRR greater than 40 dB. The peak cycle-to-cycle jitter is 25 ps at 700 MHz and a 2.8-GHz VCO frequency with a 500-mV step on the regulator's 3.3-V supply. The total power dissipated by the prototype is 130 mW and its active area is 1.48/spl times/1.00 mm/sup 2/.

任意精度向き準並列形高速除算機構

任意精度向き準並列形高速除算機構

Design and VLSI evaluation of a high-speed cellular array divider with a selection function

In recent years, very fast dividers have been required for the real-time application of digital signal processing, robot control, and the like. This paper proposes a high-speed cellular array divider with a selection function that is based on the non-restoring algorithm and can deal with both fixed-point and negative operands in two's complement form. This divider uses new techniques that can generate in parallel both the quotient bit of one row and a partial remainder and CLS bit of the next row. The delay time of the proposed divider is calculated in terms of a delay of one unit such as a NAND gate. Finally, by using PARTHENON, a CAD (computer-aided design) system for VLSI, this divider is designed and evaluated. As a result, elimination of the delay time for even rows becomes possible. Thus, the delay time can be decreased to approximately one half that of the high-speed divider proposed by Cappa and Hamacher, which uses the most general high-speed techniques of carry-save and CLA.

高基数に基づく選択型高速除算器の構成

高基数に基づく選択型高速除算器の構成

Built-in self-test (BIST) design of high-speed carry-free dividers

This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labeling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. For the BIST design of a 64 b C-testable divider, its hardware overhead is less than 5%.

Design and test generation of C-testable high-speed carry-free dividers

Presents a C-testable carry-free divider circuit design and its test generation. The divider circuit takes the dividend digits, in redundant binary form, and divisor digits, in binary form, as its inputs and produces the quotient and remainder digits, also in redundant binary form. The circuit is fully testable with a test set of 72 test patterns irrespective of its bit size. To generate the test patterns and the corresponding control signals easily, a graph labelling scheme is employed to derive a set of simple labels for the dividend, the divisor, the quotient, the remainder and the control signals.

Concurrent-error detection in high-speed carry-free dividers

Rapid advancements in technology demand innovative computation algorithms and hardware structures to achieve high performance. High-speed dividers are commonly designed using SRT division methods. Recently, a high-speed carry-free divider design using redundant binary representation has been presented. Based on the carry-free division algorithm and a more general cell-fault model instead of stuck-at fault model, the paper presents a concurrent error detection scheme using alternating input data. The key to the detection of faults is determining that at least one input combination exists for which the error does not result in alternating outputs. Results show that, with a low hardware overhead, the divider circuit is capable of detecting single/multiple transient faults in one cell during the real-time operation and enhancing its reliability significantly.

Novel carry propagation in high-speed synchronous counters and dividers

A high-speed binary counter and a divider using a new carry propagation scheme is presented. The critical logic depth is one and the maximum fan-in of gates can be reduced to two, independent of the number of bits in both the counter and the divider. The hardware grows linearly with the number of bits, making them well suited for a wide range of applications.

High-speed division unit using asymmetric neural network architecture

A neural network with symmetric synaptic connections has been shown to be an effective computational unit. However, this model does not always guarantee global convergence nor yield a fast settling time. An asymmetric model without these problems is introduced in the letter. A high-speed divider illustrates its computational capabilities.

Study on GaAs monolithic dynamic divider

AbstractThe GaAs monolithic dynamic divider, a high speed divider for microwave phase locked oscillators, has been studied. It can be operated at a higher speed than static dividers. The load in the inverter section is a passive resistor. Improved circuit topology at interstage buffers and reduction of gate resistance by the Au/WSi self‐aligned process have been used for superior characteristics of a single FET. For a 1 μm gate length, both division and frequencies ranging from 4.3 GHz to 7.3 GHz have been observed. As a system application, the divider has been implemented in a 13 GHz frequency synthesizer of oscillator‐multiplier type. The divider has been operated in the 6.5 GHz band and an operation with 1 MHz steps has been confirmed at the 13 GHz band. The phase noise has been 90 dBc/Hz at the off‐carrier frequency of 10 kHz. This value is sufficient for conventional microwave circuits.