High-speed Divider Research Articles

High-speed and low-power GaAs DCFL divider

High-speed and low-power divide-by-252 or -256 circuit have been fabricated by using high-transconductance GaAs enhancement-mode MESFETs. This variable-modulus divider is able to operate up to a clock frequency of 3.7 GHz. The total power dissipation at the maximum frequency is 180 mW, and it is as low as 42 mW and 30 mW at 3 GHz and 2.5 GHz, respectively.

High-speed GaAs SDFL divider circuit

High-speed divider circuits find numerous applications in prescalers for counters, frequency synthesizers, and digital phase locked loops. To accommodate these applications, a high-speed multimode divider circuit has been designed, fabricated, and tested. This circuit, fabricated on semi-insulating Gallium Arsenide substrates, and utilizing Schottky diode FET logic (SDFL) technology, has been tested at a maximum clock frequency of 1.84 GHz. High yields of circuits operating over 1 GHz have been obtained over a number of wafers.

High-Speed GaAs SDFL Divider Circuit

High-speed divider circuits find numerous applications in prescalers for counters, frequency synthesizers, and digital phase locked loops. To accommodate these applications, a high-speed multimode divider circuit has been designed, fabricated, and tested. This circuit, fabricated on semi-insulating Gallium Arsenide substrates, and utilizing Schottky diode FET logic (SDFL) technology, has been tested at a maximum clock frequency of 1.84 GHz. High yields of circuits operating over 1 GHz have been obtained over a number of wafers.

Design of High-Speed Digital Divider Units

The division operation has proved to be a much more difficult function to generate efficiently than the other elementary arithmetic operations. This is due primarily to the need to test the result of one iteration before proceeding to the next. The technique described in this contribution reduces the iteration time by the use of a redundant quotient representation, which avoids the need to complete the arithmetic operation. A borrow–save subtractor (analogous to a carry–save adder) can then be used for the arithmetic. Further improvement is obtained by use of a lookahead decoding technique. Cost reductions are obtained either by use of uncommitted logic arrays, or by a novel borrow–save system using commercially available adder circuitry. A comparison of a number of divider units with a wide range of cost and speed is included.

High-speed divider using multiplication

With the rapid development of semiconductor IC technology, particularly in the field of very large scale integration (VLSI), high-speed monolithic parallel multipliers are functional blocks that may one day find wide acceptance. The authors describe the implementation of an iterative division algorithm using a 16-bit monolithic multiplier. The basis of the division algorithm is the Newton-Raphson iterative method, which is slightly modified here in order to adapt to the multiplier performance characteristics and to further simplify the hardware complexity. The article also shows that by applying a suitably chosen initial iterate, the desired result is obtained in a single iteration.

Reduction of 'phosphor noise' in cathode-ray tube film scanners

A high-speed analogue divider was built and incorporated into the video output circuit of a cathode-ray tube film scanner. This is shown to be an effective technique for minimizing spurious noise introduced by local variations in the light output from the phosphor.

A static magnetic transistor analogue divider

RECTANGULAR loop magnetic materials and transistors used as switches have been combined to produce a simple, high-speed analogue divider. This device is capable of producing an output whose average voltage is the quotient, with the correct sign, of two input voltages. A preliminary model of this divider gives accuracies of ±2.5 per cent of full scale readings for a quotient range of 100 to 1 and input variations of both numerator and denominator of better than 10 to 1.