Abstract
High speed divider is highly desired in the millimeter wave (mmW) frequency synthesizer design. A high operating frequency, low power consumption 90-nm CMOS programmable pulse swallow multi-modulus-divider is presented in this paper. High speed true-single-phase-clock D-flip-flop (TSPC DFF) is used in the counter in order to obtain a high operating frequency. It can operate at a frequency range from 4.1 GHz to 9.2 GHz, with a division ratio of 101–164. It has a power efficiency of 3.1 GHz/mW, and it can be used to provide a high quality reference frequency in the mmW phase-locked loop.
Highlights
Due to the requirement of modern high-rate communication, ultra-wide-band transceivers are of demand
A Σ − ∆ modulator is used in the chip for providing a division ratio of MMD, and it can be used for fraction division in the PLL, it is controlled by a serial peripheral interface (SPI), which provides a division ratio of eight-bit integer and 24-bit decimal
Fabricated in TSMC 90 nm CMOS technology, the chip photo of MMD and test structure is shown in Figures 9 and 10
Summary
Due to the requirement of modern high-rate communication, ultra-wide-band transceivers are of demand. To generate a high quality carrier signal for modulating and demodulating in the transmitters and receivers is a challenge in the mmW integrated circuit design [1]. Phase-locked-loop (PLL) is always used to generate a carrier signal. It can multiply a low reference frequency by a ratio to obtain a high frequency signal [2,3,4]. The usage of PLL is more and more important in mmW circuit design like 5G communication system and radar, as the quality of the signal is important in modulating and demodulating in the transmitter and receiver. A divider is an important part in the PLL system, it divides the high-frequency signal from the output of the voltage-controlled oscillator (VCO) to the reference frequency [5]
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