High-speed Design Research Articles

Research on Design Method of High Speed and High Dynamic Pressure Separation Structure

The inter-stage separation scheme has always been the focus and difficulty of low-altitude high-speed aircraft design. The separation reliability of low altitude high-speed aircraft is required to be higher. Experts and scholars have carried out design research on different forms of separation schemes. In this paper, two typical kind of inter-stage separation schemes are introduced. For aircraft A, a point cold separation scheme is adopted, which is connected by four explosive bolts, and two piston push rods provide separation impulse. For aircraft B, exhaust ports are opened on both sides of the rear of the transition section. The tail section is equipped with four “X” full-motion rudders for flight control. In addition, two horizontal stabilizers were added to improve stability. Based on the comparison and analysis of different inter-stage separation schemes for The separation reliability of low altitude high-speed aircraft is required to be higher. Experts and scholars have carried out design research on different forms of separation schemes. two different types of aircraft A and aircraft B, a new high reliability interstage separation scheme is proposed, the feasibility of the scheme is verified by simulation analysis, and the design of the stage separation structure under high dynamic pressure and high speed with compact layout is realized.

Design of High Speed and Low Power Differential Voltage Charge Sharing Comparator using Small Swing Domino Logic

Design of High Speed and Low Power Differential Voltage Charge Sharing Comparator using Small Swing Domino Logic

PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices

With the rapid growth in design and fabrication outsourcing in semiconductor industry, concerns have increased about insuring the trustworthiness of underlying hardware, commonly known as hardware Trojans. This paper presents a new low-cost and high-speed design for trust methodology (DfTr) to detect hardware Trojans, especially for resource-constraint IoT devices. To relieve the stealthy nature of Trojans, the full controllable paths are created between the low transition probability nets and the primary inputs. The key idea is that instead of specifying the full controllable paths based on minimum logical depth, one can alternatively specify the paths with the aim of achieving minimum number of insertion-points to lower the area overhead in devices with limited hardware resources. Accordingly, this paper develops a formal Property-based design modification mechanism, called PODEM, targeting different objective functions so as to lower the area overhead as well as augmenting the hardware Trojan detection sensitivity. The experimental results on different benchmark circuits show that the number of required insertion-points for the proposed methodology is favorably decreased around 28% compared with the state-of-the-art method. In addition to the lower area and delay overheads, the side channel detection sensitivity of the proposed approach is also augmented about 11.5%, on average, thanks to the considerable reduction of 18.7% in the background circuit activity.

A Stepped-Segmentation Method for the High-Speed Theoretical Elevator Car Air Pressure Curve Adjustment

As the demand for high-speed elevators grows, the requirements of elevator performance have also increased. Most of these are single variables that do not consider the comprehensive impact of multiple variables on performance, especially comfort. To overcome this problem, a stepped segmentation method for a theoretical high-speed elevator car air pressure curve (THEC-APC) adjustment is proposed that could actively help to select a suitable theoretical elevator car air pressure adjustment curve. By utilizing the proposed Particle Swarm Optimization (PSO) algorithm, the theoretical elevator car air pressure curve is optimized for multiple performances (including passenger comfort, energy consumption, and aerodynamic characteristics). In addition, the THEC-APC is smoothed by the Bezier curve for the variable destination floor. To verify the proposed method, the KLK2 (Canny Elevator Co., Ltd., 2015, Suzhou) high-speed elevator design process is applied. The numerical experiment results show that the proposed method can improve the accuracy and search efficiency of the optimal solution. Meanwhile, the proposed method helps to promote further air pressure compensation design for high-speed elevators.

SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage

Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die that does not cause SRAM read and write failures, which are majorities of SRAM failures, under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, Vfail, that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM Vˆddmin on each die from the measured Vfail of SRAM monitor on the same die where Vfail-Vddmin correlation table is built-up in design infra development phase, and Vˆddmin can be directly derived from the measured Vfail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 10.45%, read energy by 4.99%, and write energy by 5.45% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint. In addition, the effect of IR drop and process variations of peripheral circuit on Vddmin prediction is taken into account by reflecting them on SRAM bitcell operation. We also solidify our Vddmin prediction methodology by considering the prevention of potential SRAM access failures for high-speed designs as well as the SRAM read and write failures.

Investigation of spindle-tool assembly dynamics for optical grinding motorized spindles

Advanced optical systems have brought forward higher requirements for aspheric processing of hard brittle materials, which put forward higher request to the dynamic performances of optical grinding spindles. Due to the integration of the spindle and the tool of optical machine systems, the dynamic behaviors of the spindle system are more complicated than that of other spindles. An integrated model dynamic model of optical grinding motorized spindles which consists of a bearing model, a thermal model and a spindle-tool dynamic model is proposed. The bearing model takes the effect of the thermal displacement into account, and the rotor dynamic model with the effects of the tool and damp is established by the finite element method (FEM). An example calculation on a grinding motorized spindle is preformed and the correlative test is carried out. In the process, the dynamic model is modified by the free excitation test. The mathematical results agree well with the experimental data, which indicates that the proposed model is able to analyse the bearing-spindle-tool assembly dynamics of optical grinding motorized spindles. Meanwhile, the influences of the thermo-mechanical coupled factor (TMCF) and the tool on the dynamic behaviors of the system are obtained. The conclusions are available to the dynamic analysis and design of various high speed and precision spindles.

Friction Stir Welding in the Aircraft Production

The paper presents the results of experimental development of the technology of friction stir welding to obtain a nonseparable connection of a special aerospace aluminum, titanium and magnesium alloys, high-temperature steels. Regularities and models of heat balance in the welding zone have been determined, which make it possible to predict the technological possibilities of high-speed friction welding. It is established that high-speed friction welding by mixing allows to obtain a high-quality connection at lower loads on the design of the equipment. On the basis of studies of macro-and microstructure, microhardness, level of residual stresses and strength tests, technological recommendations on the choice of welding conditions and conditions were obtained. Presented of experimental and industrial development of special equipment, high-speed friction welding, design and manufacturing of high hardness tools of complex spatial shapes for welding aircraft materials.

Design of High Speed and Precision and Low-Power LVDS Driver for CMOS Image Sensor

Aiming at the requirement of high speed and precision, low-power and large-capacity load of serial data interface for aerospace super large array(15k×15k) CMOS image sensor, a design scheme low voltage differential signal (LVDS) driver by combining the split-length method with the pre-emphasis technique is proposed. Firstly, comparing with the general design schemes, the present scheme uses the split-length compensation method to increase effectively the unity-gain bandwidth while keeping the op-amp gain constant. Secondly, the pre-emphasis technique is used to compensate the LVDS driver for high-frequency components to improve the driving capability of the capacitive load and high speed signal integrity (SI). The simulation results show that the accuracy of the common-mode feedback voltage is improved by using the split-length compensation method, and also the common-mode voltage changes below 15 mV. The pre-emphasis technique is used to enhance the amplitude of the high-frequency components lost during the high-speed transmission. The quality of the signal eye diagram during high-speed transmission reduces the bit error rate, and both the transmission rate and the driving load capacity are two times more than the general design (1.2 Gb/s@12 pF), and the quiescent current consumption is only 4.6 mA@12 pF. The present LVDS driver design is implemented in a typical CMOS process of 0.18 μm.

Comprehensive and Practical Way to Look at Far-End Crosstalk for Transmission Lines With Lossy Conductor and Dielectric

Far-end crosstalk (FEXT) noise is one of the major issues that limits signal integrity performance for high-speed digital products. It is important to estimate the crosstalk noise accurately to avoid noise margin failure or overdesigned transmission lines. Traditionally, analytical formulas for crosstalk noise are based on lossless and perfect impedance match assumptions, which provide limited guidance for a practical high-speed transmission line design. A phenomenon is observed that a lossy conductor increases the FEXT on coupled striplines. To provide a reasonable explanation, analytical and numerical investigations were performed using a modal analysis based approach. A new FEXT component due to the lossy conductor is proposed. Such FEXT component is important to a high-speed stripline design because it is a major contributor when all terminals are matched. To estimate the impact of loss on FEXT, a practical and fast estimation approach is proposed.

The Design of Low Power High Speed Two Level Three input XOR gate

The Large Fan-In and high performance gates are essential to make portable electronic devices. In this paper an efficient realization of three input two level XOR(Exclusive-OR) is presented. The design of low power and high speed proposed XOR gate involves the combination of pass and transmission gates. The main objective to achieve this is based on the selection of input signals to propagate and maintain the good logic swing. Two methods were used to design proposed XOR, one (i.e. Pass_gate) is purely based on pass transistors with 8 MOSFET’s and second method(Modified_Pass_gate) uses transmission gates with 12 transistors. The Modified_Pass_gate offers 86.14% and 6.66% of power dissipation reduction compared to static and Pass_gate XOR respectively and 77.18% and 50.94% less propagation delay compared to static and Pass_gate XOR respectively, at the supply voltage of 0.7v with input signal frequency of 3GHz. The simulation is performed based on 32nm technology node(PTM-models) using Hspice Synopsis simulation tool.

Design and Implementation of Vlsi Architecture for Arrhythmia Detection

Arrhythmia is one in all the foremost well-liked heart diseases that might result in serious consequences. In case of arrhythmia, the heart rate may be either too fast or slow. When a person suffers from arrhythmic the heart may not pump sufficient blood to all body parts that is necessary for circulation. some of the symptoms of arrhythmia includes faintness ,fluttering your chest, a light headedness or dizziness, fainting or near fainting and on the worst it may turn out to be deadly causing ventricular fibrillation. Due to this it is very crutial to detect conditions of arrhythmia. It is very difficult to identify the symptoms of arrhythmia from a long ECG record. This projects presents a VLSI based design of high speed and minimum area for arrhythmia detection .It uses arithmetic distribution discrete wavelet transform for arrhythmia detection of QRS wave and is implemented using CADENCE. The purpose of distributive arithmetic discrete wavelet change is to compress the ECG signal. ECG signals are generated via MATLAB. The resultant of these coefficients are given to the LUT, which comprises of MIT-BIH databases. Our aim is to detect the QRS complex in the ECG signal and to identify the time and frequency variations. By comparing these variations with that of the reference variations produced in the normal ECG waveform it is easy to identify whether the patient is suffering from arrhythmia or not. The coding was written in verilog and stimulated in modelsim software and implemented using CADENCE tool.

Limited Angle Electrical Resistance Tomography in Wastewater Monitoring.

Electrical resistance tomography (ERT) has been investigated in monitoring conductive flows due to its high speed, non-intrusive and no radiation hazard advantages. Recently, we have developed an ERT system for the novel application of smart wastewater metering. The dedicated low cost and high-speed design of the reported ERT device allows for imaging pipes with different flow constituents and monitoring the sewer networks. This work extends the capability of such a system to work with partially filled lateral pipes where the incomplete data issue arises due to the electrodes losing contact with the conductive medium. Although the ERT for such a limited region has been developed for many years, there is no study on imaging content within these limited regions. For wastewater monitoring, this means imaging the wastewater and solid inclusions at the same time. This paper has presented a modified ERT system that has the capacity to image inclusions within the conductive region using limited data. We have adjusted the ERT hardware to register the information of the non-contact electrodes and hence the valid measurements. A limited region image reconstruction method based on Jacobian reformulation is applied to gain robustness when it comes to inclusion recovery in limited data ERT. Both simulation and experimental results have demonstrated an enhanced performance brought by the limited region method in comparison to the global reconstruction.

High-Speed Plasmonic-Silicon Modulator Driven by Epsilon-Near-zero Conductive Oxide

Transparent conductive oxides (TCOs) such as indium-tin oxide (ITO) have attracted increasing interests in integrated photonics and silicon photonics, owing to their large plasma dispersion and epsilon-near-zero (ENZ) effect. The nonlinear change of refractive index induced by free carrier modulation leads to a large electro-optic modulation with ultra-compact device footprint and unprecedented energy efficiency. However, high-speed modulation result is rare, mainly due to the lack of high-speed device design and fabrication quality. In this article, we characterize the fundamental electro-optic modulation structure consisting of Au/ITO/oxide/p-Si capacitor, showing that the property of ITO is greatly affected by the process condition. We also report an 8-μm-long hybrid plasmonic-silicon modulator driven by an ENZ ITO capacitor, achieving 100fJ/bit energy efficiency, 3.5 GHz modulation bandwidth, and 4.5 Gb/s data rate. The electro-absorption modulator covers a broad optical bandwidth from 1515 to 1580 nm wavelength. For future development of such modulators, we point out that by replacing ITO with higher mobility TCO materials, we can achieve 40 GHz modulation bandwidth and 0.4 fJ/bit energy efficiency using a 3-μm-long device.

High‐speed energy efficient process, voltage and temperature tolerant hybrid multi‐threshold 4:2 compressor design in CNFET technology

Compressors are fundamental components in multi-operand addition and multiplication hardware. The present study aims to propose several high-speed hybrid designs of 4:2 compressors which are implemented based on multi-threshold logic and transmission gate multiplexers, at low supply voltages. In order to implement these circuits, carbon nanotube field-effect transistors (CNFETs) are utilised. The division of the entire input capacitor network in the third proposed design causes the entire structure operates faster and consumes less power. All designs were simulated with Synopsys HSPICE and 32 nm CNFET technology in different conditions. Simulation results demonstrate the superiority of the third proposed design with regard to different load and frequency conditions. In addition, it becomes less sensitive to process, voltage and temperature variations compared to other similar capacitive threshold logic circuits. The results indicate the third proposed design outperforms the best reference design in terms of delay and power-delay product by 34 and 25%, respectively. Furthermore, the performance of each design was evaluated in a 8 × 8-bit binary multiplier as a uniform test bench, which confirmed the above results on isolated single 4:2 compressors.

RETRACTED ARTICLE: Memristor based high speed and low power consumption memory design using deep search method

The demand for low-power devices in today’s world is increasing, and the reason behind this is scaling CMOS technology. Due to scaling, the size of the chip decreases and the number of transistors in System-On-Chip increases. However, transistor miniaturization also introduces many new challenges in circuit design for very large scale integrated circuits. Therefore in this work is introduced a memristor based memory design, the memristor breaks the scaling limitations of CMOS technology and prevails over emerging semiconductor devices. The memristor is forced to the Nano scale design of the invention, and successful fabrication begins to take into account the range of conventional metal oxide semiconductor field effect transistors or more specifically the use of transistors as a whole. The memristor has a history mechanism that allows the memory operation to be combined with the inherent bipolar resistance switching characteristics. Different types of existing mathematical models have been derived from shapes that can be further implemented and tested in a prototype with some crucial parameters thus determined and how they differ from conventional transistor-based designs for a suitable circuit memristor. In this work, low-power complementary metal oxide semiconductor (CMOS) flip-flops have been proposed with deep search pattern method and some key parameters such as delay, power, gate count and other memristor calculations are carried out. The simulations are carried out using Verilog-analog mixed signal. The proposed system is considered as potential devices for building memories because they are very dense, non-volatile scalable devices with faster switching times and low power dissipation and are also compatible with the existing CMOS-technology.

Ultra high speed and novel design of power-aware CNFET based MCML 3-bit parity checker

MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for competent and novel substances to overcome the shortcoming of existing silicon. The future technology should be capable to deliver fast response, low power operation, scalable to reduced dimensions, and strong towards process variations. Carbon nanotube based technology (CNFET) is one of the reliable and competent alternative because it has most of these desired features and similar operating principle as that of CMOS. And hence, this research article focuses on a relative evaluation of CMOS and CNFET version of 3 bit parity checker at 16-nm technology nodes. The CNFET based 3 bit parity checker is faster (9.75×), it offers improvement in power dissipation (11.93×), improvement in PDP (116.39×), improvement in EDP (1135.76×) compared to CMOS counterpart. Scaling down the device emerges with a challenge of variability, just as power, delay and area, variability also has an impact on performance of the circuit. Technology scaling has significant consequences such as wider variation. This research article also presents variability analysis, in terms of delay (tp) and power-delay product (PDP) for the proposed CNFET based MCML 3 bit Parity checker circuit. Extensive simulation using 16-nm technology node are carried out by loading two nominal copies of 'CNFET based MCML 3 bit Parity checker' (Circuit under Test) at either ends—input and output. This simulation framework supports the high level integration where stand alone operation has no application in the industry. The intent of this research is to investigate the circuit with minimal variability to propagation delay and PDP. The proposed ‘CNFET based MCML 3 bit parity checker’ exhibits improvement in delay (14.01×) and improvement in PDP (242.1×) variability as compared to CMOS counterpart. Thus, the CNFET based implementation emerges out as a robust circuit showing narrower spread in variability analysis against applied VDD.

HSRDN: High‐Speed Router Design for Various NoC Topologies

High-speed router design for network on chip (HSRDN) is proposed for controlling the traffic congestion and deadlocks. Diagonal based nearest-path routing algorithm for NoC (DNRAN) can mitigate the effect of latency by opting for the nearest-path to reach the destination in a network and HSRDN is part of DNRAN. When we analyze the performance of DNRAN for all proposed topologies, nearly 50% better in terms of latency reduction and high throughput over existing router architectures. The proposed topologies (2D-mesh, 2D-Star mesh over regional mesh (SMoRM), 3D-mesh, and 3D-torus) are tested with various applications, viz, audio, video and so on. Here, we also tested with cryptography application for DNRAN. When we analyzed the performance of experimental results, exclusively in 2D-SMoRM nearly 0.6 times latency get reduced, area expanded by 0.25 and 0.33 times throughput increase in 2D-SMoRM compared with 3D-mesh and 3D-torus. Therefore, DNRAN showed an exclusive performance in 2D-SMoRM compared with other two topologies.

Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond

This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization. Seven key device design parameters and their multiple impacts on a 6T SRAM cell are systematically evaluated, focusing on materials band engineering, device design, circuit parameters tradeoff, and variation control. The area of SRAM cell under the same Fin quantization scheme remains constant in all evaluations. To the best of our knowledge, the most comprehensive discussion about circuit optimization from multiple device design parameters perspective is presented. Based on our cooptimization scheme, a SRAM cell is effectively designed. For a low-power and robust SRAM cell design, we achieve 56.7% reduction in leakage, 7.9% improvement in hold noise margin (HNM), 8.6% improvement in read noise margin (RNM), and 10.8% improvement in write margin (WM) at the expense of 19.3% increase in delay under design space of gate length (Lg) and spacer thickness (TSPC). For a high-speed SRAM cell design, we recommend focusing on the optimization of architecture and peripheral circuits. This framework not only has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.

Design of a Voltage to Time Converter with High Conversion Gain for Reliable and Secure Autonomous Vehicles

Automation of vehicles requires a secure, reliable, and real-time on-chip system. These systems also require very high-speed and compact on-chip analog to digital converters (ADC). The conventional ADC cannot fulfill this requirement. In this paper, we proposed a Darlington pair- and source biasing-based high speed, secure, and reliable voltage to time converter (VTC). It is a compact, high-speed design and gives high conversion gain. The source biasing also helps to increase the input voltage range. The conversion gain of the proposed circuit is 101.43ns/v, which is 52 times greater than the gain achieved by state-of-the-art design. It also shows less effect of process variation and bias temperature instability.

How Can Si/Ge Core/Shell Nanowires Outperform Their Pure Material Counterparts?

Si/Ge core/shell nanowires have been demonstrated to be a promising candidate for the next-generation transistor channel. The tunable electron and hole transport paths improve their mobilities significantly. Here, we comparatively investigate the electronic properties of the Si-core-Ge-shell and Ge-core-Si-shell nanowires and their pure material counterparts using the first-principles method. The effects of core/shell ratio, atom number, and cross-sectional shape are studied. The Si-core-Ge-shell nanowires show excellent transport path separation and small carrier effective mass properties when the core/shell ratios exceed 0.5. For smaller ratios, the energies of the off- $\Gamma $ valleys in the Ge shells are lowered and become the conduction band minimum (CBM) because of the intrinsic strains along the radial direction, enlarging the electron effective masses significantly. To restrain this effect, the uniaxial strain engineering is adopted and the best performance is exhibited when 2%–3% tensile strains are applied. In the Ge-core-Si-shell nanowires, both electrons and holes are easily confined to the core region. Compared with the Si-core-Ge-shell nanowires, their energy gaps and electron effective masses are smaller and larger, indicating poor transportability. The above discoveries are further validated by changing the cross-sectional shapes of the nanowires and device performance simulations, confirming that the Si-core-Ge-shell nanowires can outperform their pure material counterparts in high-speed transistor designs.