Abstract

With the rapid growth in design and fabrication outsourcing in semiconductor industry, concerns have increased about insuring the trustworthiness of underlying hardware, commonly known as hardware Trojans. This paper presents a new low-cost and high-speed design for trust methodology (DfTr) to detect hardware Trojans, especially for resource-constraint IoT devices. To relieve the stealthy nature of Trojans, the full controllable paths are created between the low transition probability nets and the primary inputs. The key idea is that instead of specifying the full controllable paths based on minimum logical depth, one can alternatively specify the paths with the aim of achieving minimum number of insertion-points to lower the area overhead in devices with limited hardware resources. Accordingly, this paper develops a formal Property-based design modification mechanism, called PODEM, targeting different objective functions so as to lower the area overhead as well as augmenting the hardware Trojan detection sensitivity. The experimental results on different benchmark circuits show that the number of required insertion-points for the proposed methodology is favorably decreased around 28% compared with the state-of-the-art method. In addition to the lower area and delay overheads, the side channel detection sensitivity of the proposed approach is also augmented about 11.5%, on average, thanks to the considerable reduction of 18.7% in the background circuit activity.

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