High-speed Decoder Research Articles

A Novel Quasi-Cyclic LDPC Codes Construction Method for High-Speed Parallel Decoding

The decoding parallelism of quasi-cyclic low density parity check (QC-LDPC) codes, an important realization factor of LDPC codes, is limited by the block size. Joint row-column (JRC) decoding algorithm, an efficient decoding technique having low computation cost and small iteration number, also suffers from the decoding parallelism limitation in QC-LDPC application. In this paper, a novel LDPC-code construction method is presented and validated. This method constructs the row sets to eliminate the data access conflicts, and it clearly enhances the decoding parallelism while avoids any degradation of bit error rate (BER) performance.

High-Speed Decoding of the Binary Golay Code

Recently, some table-lookup decoding algorithms (TLDAs) have been used to correct the binary Golay code. Thispaper proposes an efficient high-speed TLDA called message-syndrome decoding algorithm (MSDA) by using themessage syndrome to correct the binary systematic Golay code. The proposed MSDA is based on the novelmessage-syndrome lookup table (MSLT). The MSLT merely consists of 12 candidate syndromes and its memory sizeis significantly smaller than other existing lookup tables. Computer software simulation results show that the decodingspeed of the proposed MSDA is superior to other proposed TLDAs.

Turbo Code Design and Implementation of High-Speed Parallel Decoder

Due to the high complexity Turbo decoding algorithm, implemented the hardware decoder logic of consumes more resources and storage resources, decode delay larger. In order to meet LTE systems, high reliable transmission of high data rate needs high speed Turbo decoder design faces enormous challenges. This topics select based on LTE system of parallel Turbo Code decoders hardware design and achieved as research direction, select FPGA(Virtex-6) as hardware design and achieved of platform, from Log-MAP algorithm of Sentinel of, and State measure value handed owned calculation in the of owned a of processing, and Diego generation decoding algorithm of parallel of, and parallel interwoven Manager design, and key path optimization technology, aspects analysis, design achieved has LTE Turbo Code high-speed parallel decoders. DOI: http://dx.doi.org/10.11591/telkomnika.v11i4.2393 Full Text: PDF

Algebraic decoding of the binary systematic (71, 36, 11) quadratic residue code

A fast and efficient algebraic decoding algorithm (ADA) is proposed to correct up to five possible error patterns in the binary systematic (71, 36, 11) quadratic residue (QR) code. The technique required here is based on the ADA developed by He et al. [2001. Decoding the (47, 24, 11) quadratic residue code. IEEE transactions on information theory, 47 (3), 1181–1186.] and the modification of the ADA developed by Lin et al. [2010. Decoding of the (31, 16, 7) quadratic residue code. Journal of the Chinese institute of engineers, 33 (4), 573–580; 2010. High speed decoding of the binary (47, 24, 11) quadratic residue code. Information sciences, 180 (20), 4060–4068]. The new proposed conditions and the error-locator polynomials for different numbers of errors in the received word are derived. Simulation results show that the decoding speed of the proposed ADA is faster than the other existing ADAs.

멀티미디어 기반 해상통신을 위한 DVB-S2 기반 고속 LDPC 복호를 위한 알고리즘에 관한 연구

본 논문에서는 멀티미디어 기반의 해상통신을 위한 DVB-S2 기반 고속 LDPC 복호를 위한 알고리즘을 제안하였다. 체크 노드 연산중에 비트 노드 연산을 수행하여 기존의 LDPC 복호 알고리즘에 비해 반복횟수를 줄일 수 있는 horizontal shuffle scheduling 알고리즘을 기반으로 하여 복호 속도를 보다 고속화 할 수 있는 알고리즘을 제안하였다. 기존의 체크 노드 연산은 하나의 메모리에서 값을 가져오기 때문에 체크 노드 연산과정에서 많은 지연이 발생하는데 이를 dc개의 병렬구조로 설계함으로써 체크 노드 연산과정의 지연을 줄일 수 있고 따라서 고속 복호가 가능하다. 이를 시뮬레이션 한 결과, 최대 반복 30회를 수행하였을 때 HSS 알고리즘은 326 Mbit/s, 제안한 알고리즘은 2.29 Gbit/s로 약 7배 이상의 복호 throughput을 얻을 수 있었다. In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

HSS 기반 초고속 LDPC 복호를 위한 구조

본 논문은 위성방송 전송 규격인 DVB-S2의 기반 채널 부호로 사용되는 LDPC를 고속 복호를 위해 HSS(Horizontal Shuffle Scheduling) 방식을 기반으로 고속 복호기 구조를 연구하였다. 첫째로 HSS방식에서 발생하는 메모리 충돌을 극복하는 방식을 제시한다. 둘째로 고속 복호를 위해 LUT(Look Up Table)을 이용하는 Sum-Product 알로리즘 대신 min값에서 scaling factor를 곱하는 Normalized Min-Sum 알고리즘을 사용하였으며, 성능 향상을 위해 check node에서 bit node로 입력되는 값의 부호를 확인하여 신뢰성 없는 값을 삭제하는 Self-Correct 방식을 제시하여 sum-product 방식에서 발생하는 bottle neck 현상을 하였다. 마지막으로 고속화를 위한 효율적인 메모리 구조를 제안한다. This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc<TEX>${\rightarrow}$</TEX>v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'<TEX>${\rightarrow}$</TEX>c and the sign of the previous incoming messages Moldv'<TEX>${\rightarrow}$</TEX>c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

High-speed and parallel approach for decoding of binary BCH codes with application to Flash memory devices

In this article, we propose a high-speed decoding algorithm for binary BCH codes that can correct up to 7 bits in error. Evaluation of the error-locator polynomial is the most complicated and time-consuming step in the decoding of a BCH code. We have derived equations for specifying the coefficients of the error-locator polynomial, which can form the basis for the development of a parallel architecture for the decoder. This approach has the advantage that all the coefficients of the error locator polynomial are computed in parallel (in one step). The roots of error-locator polynomial can be obtained by Chien's search and inverting these roots gives the error locations. This algorithm can be employed in any application where high-speed decoding of data encoded by a binary BCH code is required. One important application is in Flash memories where data integrity is preserved using a long, high-rate binary BCH code. We have synthesized generator polynomials for binary BCH codes (error-correcting capability, s) that can be employed in Flash memory devices to improve the integrity of information storage. The proposed decoding algorithm can be used as an efficient, high-speed decoder in this important application.

A Pragmatic Coded Modulation Scheme for High-Spectral-Efficiency Fiber-Optic Communications

A pragmatic coded modulation system is presented that incorporates signal shaping and exploits the excellent performance and efficient high-speed decoding architecture of staircase codes. Reliable communication within 0.62 bits/s/Hz of the estimated capacity (per polarization) of a system with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> =2000 km is provided by the proposed system, with an error floor below 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-20</sup> . Also, it is shown that digital backpropagation increases the achievable spectral efficiencies-relative to linear equalization-by 0.55 to 0.75 bits/s/Hz per polarization.

Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes

Generalized minimum distance (GMD) decoding of Reed---Solomon (RS) codes can correct more errors than conventional hard-decision decoding by running error-and-erasure decoding multiple times for different erasure patterns. The latency of the GMD decoding can be reduced by the Kotter's one-pass decoding scheme. This scheme first carries out an error-only hard-decision decoding. Then all pairs of error-erasure locators and evaluators are derived iteratively in one run based on the result of the error-only decoding. In this paper, a more efficient interpolation-based one-pass GMD decoding scheme is studied. Applying the re-encoding and coordinate transformation, the result of erasure-only decoding can be directly derived. Then the locator and evaluator pairs for other erasure patterns are generated iteratively by applying interpolation. A simplified polynomial selection scheme is proposed to pass only one pair of locator and evaluator to successive decoding steps and a low-complexity parallel Chien search architecture is developed to implement this selection scheme. With the proposed polynomial selection architecture, the interpolation can run at the full speed to greatly increase the throughput. After efficient architectures and effective optimizations are employed, a generalized hardware complexity analysis is provided for the proposed interpolation-based decoder. For a (255, 239) RS code, the high-speed interpolation-based one-pass GMD decoder can achieve 53% higher throughput than the Kotter's decoder with slightly more hardware requirement. In terms of speed-over-area ratio, our design is 51% more efficient. In addition, compared to other soft-decision decoders, the high-speed interpolation-based GMD decoder can achieve better performance-complexity tradeoff.

Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications

This paper proposes a high-speed and area-efficient three-parallel Reed-Solomon (RS) decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve a high throughput rate, the inner signals, such as the syndrome, error locator and error value polynomials, are computed in parallel. In addition, the key equations are solved by using the S-DCME algorithm to reduce the hardware complexity. To handle the many problems caused by applying the S-DCME algorithm to the KES block, we modify the architectures of some of the blocks in the three-parallel RS decoder. The proposed RS architecture can reduce the hardware complexity by about 80% with respect to the KES block. In addition, the proposed RS architecture has an approximately 25% shorter latency than the conventional parallel RS architectures.

High speed decoding of the binary (47, 24, 11) quadratic residue code

An efficient table lookup decoding algorithm (TLDA) is presented to decode up to five possible errors in a binary systematic (47, 24, 11) quadratic residue (QR) code. The main idea of the TLDA is based on the weight of syndrome, the syndrome decoder together with a reduced-size lookup table (RSLT), and the shift-search method given by Reed et al. Thus, the size of the lookup table and computational complexity in a finite field can be significantly reduced. The memory size of the proposed condensed lookup table (CLT) consists of only 36.6 Kbytes and is only about 0.24% of the full lookup table (FLT) and 3.2% of the lookup up table given by Chen et al., respectively. These facts lead to significant reduction of computational time and the decoding complexity. A simulation result shows that the decoding speed of the proposed TLDA is much faster than all existing decoding algorithms. Moreover, it can be extended to decode all QR codes, including the class of the cyclic codes when the code length is moderate. The CLT makes this new decoding algorithm suitable for hardware or firmware implementations.

Design of High-Speed Decoder for New High-Speed Bus

This paper presents a new type of high-speed error correction for the requirements of new high-Speed Bus. Use RS (255, 239). Not only optimization traditional algorithm, but also design bidirectional synchronous calculated adjoint form module, Fast B-M algorithm module. and full parallel Chien Search module. These design used in new high-Speed Bus, Larger than usual decoder designed to significantly shorten the critical path decoding, and achieve continuous decoding. In addition, this error correction system separated error detection and correction module modules, And after error detection module add intelligent control, which reduced the complexity and power consumption of equipment. The error correction system design for the requirements of the new bus which speed is above 400m / s.

High Throughput Parallel Decoding Method for H.264/AVC CAVLC

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.

Membrane Electromechanics in Biology, with a Focus on Hearing.

Cells are ion conductive gels surrounded by a ~5-nm-thick insulating membrane, and molecular ionic pumps in the membrane establish an internal potential of approximately -90 mV. This electrical energy store is used for high-speed communication in nerve and muscle and other cells. Nature also has used this electric field for high-speed motor activity, most notably in the ear, where transduction and detection can function as high as 120 kHz. In the ear, there are two sets of sensory cells: the "inner hair cells" that generate an electrical output to the nervous system and the more numerous "outer hair cells" that use electromotility to counteract viscosity and thus sharpen resonance to improve frequency resolution. Nature, in a remarkable exhibition of nanomechanics, has made out of soft, aqueous materials a microphone and high-speed decoder capable of functioning at 120 kHz, limited only by thermal noise. Both physics and biology are only now becoming aware of the material properties of biomembranes and their ability to perform work and sense the environment. We anticipate new examples of this biopiezoelectricity will be forthcoming.

Decoder Design for RS-Based LDPC Codes

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This brief studies very large-scale integration (VLSI) decoder architectures for RS-based low-density parity-check (LDPC) codes, which are a special class of LDPC codes based on Reed–Solomon codes. The considered code ensemble is well known for its excellent error-correcting performance and has been selected as the forward error correction coding scheme for 10GBase-T systems. By exploiting the shift-structured properties hidden in the algebraically generated parity-check matrices, novel decoder architectures are developed with significant advantages of high level of parallel decoding, efficient usage of memory, and low complexity of interconnection. To demonstrate the effectiveness of the proposed techniques, we completed a high-speed decoder design for a (2048, 1723) regular RS-LDPC code, which achieves 10-Gb/s throughput with only 820 000 gates. Furthermore, to support all possible RS-LDPC codes, two special cases in code construction are considered, and the corresponding extensions of the decoder architecture are investigated. </para>

Multi-Gb/s LDPC Code Design and Implementation

Low-density parity-check (LDPC) code, a very promising near-optimal error correction code (ECC), is being widely considered in next generation industry standards. The VLSI implementation of high-speed LDPC decoder remains a big challenge. This paper presents the construction of a new class of implementation-oriented LDPC codes, namely shift-LDPC codes. With girth optimization, this kind of codes can perform as well as computer generated random codes. More importantly, the decoder can be efficiently implemented to obtain very high decoding speeds. In addition, more than 50% of message memory can be generally saved over conventional partially parallel decoder architectures. We demonstrate the benefits of the proposed techniques with an application-specific integrated circuit (ASIC) design (in 0.18-mum CMOS) for a 8192-bit regular LDPC code, which can achieve 5 Gb/s throughput at 15 iterations.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

LOW-COMPLEXITY HIGH-SPEED QUASI-CYCLIC LDPC CODED MODULATION IN OFDM WIRELESS COMMUNICATION SYSTEM

This paper investigates a Low-Density Parity-Check (LDPC) coded rthogonal Frequency-Division Multiplexing (OFDM) wireless communication system based on IEEE 802.11a standard. This paper studies low-complexity high speed decoder architectures for quasi-cyclic low density parity check (QC-LDPC) codes. Algorithmic transformation and architectural level optimization are incorporated to reduce the critical path and bit error rate (BER). Enhanced partially parallel decoding architectures are proposed to linearly increase the throughput of conventional partially parallel decoders through introducing a small percentage of extra hardware. The LDPC decoding procedure is simplified without the estimation of channel noise power. Simulation results show that this algorithm is effective and the decoding performance is satisfied when maximum iteration number is 10.

Design of High-Speed CAVLC Decoder Architecture for H.264/AVC

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.

High-Speed Recursion Architectures for MAP-Based Turbo Decoders

The maximum a posterior probability (MAP) algorithm has been widely used in Turbo decoding for its outstanding performance. However, it is very challenging to design high-speed MAP decoders because of inherent recursive computations. This paper presents two novel high-speed recursion architectures for MAP-based Turbo decoders. Algorithmic transformation, approximation, and architectural optimization are incorporated in the proposed designs to reduce the critical path. Simulations show that neither of the proposed designs has observable decoding performance loss compared to the true MAP algorithm when applied in Turbo decoding. Synthesis results show that the proposed Radix-2 recursion architecture can achieve comparable processing speed to that of the state-of-the-art recursion (Radix-4) architecture with significantly lower complexity while the proposed Radix-4 architecture is 32% faster than the best existing design