Abstract
A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.
Highlights
Overcoming the variable deterioration in reliability of a communication channel in real time is a critical issue for many communication systems
Maximum likelihood method has been used in Viterbi decoding [1].The types of convolution codes qualified in the 3GPP WCDMA mobile communication system are (561,753) and (557, 663,711)
For each state in the trellis diagram of Viterbi decoding, current path metrics are obtained from current branch metric and path metrics of the previous states, which lead to current state, by executing addition, comparison and selection operations
Summary
Overcoming the variable deterioration in reliability of a communication channel in real time is a critical issue for many communication systems. Maximum likelihood method has been used in Viterbi decoding [1].The types of convolution codes qualified in the 3GPP WCDMA mobile communication system are (561,753) and (557, 663,711) It requires high decoding speed and low power consumption because of the large constraint value [2]. A k-pointer algorithm was studied for the efficient implementation of the TB-based SMU design [6] In this implementation, several memory READ operations were required in order to decode one bit. The T-algorithm requires comparison operations for finding the best path metric in each decoding stage This limits the use of the T-algorithm for high throughput applications. We compared the gates utilization, speed and power dissipation of the different implementation and suggested a low power and high speed Viterbi decoder design.
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