High-speed Circuit Design Research Articles

Design and Implementation of High-Speed Clock Recovery Circuits Based on FPGA

According to the problem that the traditional clock recovery method based on FPGA can not recover the clock of higher frequency NRZ (Non-return to zero) serial data. This paper proposed a clock recovery design that adjusts the output clock earlier or later constantly according to the phase relationship between the input data and the feedback clock. The proposed design can be implemented on the FPGA without the higher operating frequency requirement meets the demand of middle and low version FPGA clients. The circuits implemented on FPGA has been downloaded to the Xilinx Virtex5 XC5VSX50T FPGA after behavioral simulation and post-route simulation, the debugging results verified that the proposed design is effective and realizable for clock recovery of higher frequency NRZ data and realizable for FPGA.

Efficient Frequency-Domain Analysis of PEEC Circuits Through Multiscale Compressed Decomposition

The solution of mixed electromagnetic/circuit problems is important for the electromagnetic compatibility/signal integrity/power integrity system designs. The ever-increasing frequency content of signals and decrease of geometrical features requires the 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, to be used for the analysis and design of high-speed circuits. Very large systems of equations are often produced and their efficient solution can be extremely challenging. In this paper, we propose a new frequency-domain PEEC solver which is based on the adaptive cross approximation and singular value decomposition. Taking advantage of the rank deficiency of the dense partial inductance and coefficient of potential matrices, a multiscale block decomposition is adopted to explicitly compute the inverse of the admittance matrix of the PEEC circuit. The proposed approach provides both speedup and memory storage saving, while preserving the accuracy. The efficiency of the proposed method is demonstrated through its application to the PEEC modeling of typical interconnect problems.

基于SI分析的高速数字接口拓扑结构设计

为了进一步提高高速数字接口的信号完整性，文章首先介绍了几种常见的高速互连拓扑结构，并对其优劣进行简要的分析，之后利用Cadence SigXplorer PCB SI和Allegro对TMS320C0455和DDR2 (MT47H64M16)之间的高速接口电路拓扑结构进行信号完整性设计，阐述了高速电路设计过程中利用仿真工具对PCB进行前仿真的设计流程，以便于开发人员对此类高速接口的设计。In order to further improve the signal integrity in high speed digital interface, this paper firstly introduces several common high speed interconnect topologies and analyzes their advantages and disadvantages briefly. Then this paper also analyzes the signal integrity of high speed interconnect topology between TMS320C0455 and DDR2 (MT47H64M16) using SigXplorer PCB SI and Allegro and explains the design process of pre-simulation by tools of simulation in high speed circuit design. It will be helpful for designers to such high speed interface.

Statistical delay estimation in digital circuits using VHDL

The most important feature of modern integrated circuit is the speed. It depends on circuit's delay. For the design of high-speed digital circuits, it is necessary to evaluate delays in the earliest stages of design, thus making it easy to modify and redesign a circuit if it's too slow. This paper gives an approach for efficient delay estimation in the describing phase of the circuit design. The method can statistically estimate the minimum and maximum delay of all possible paths and signal transitions in the circuit, considering the practical implementation of circuits, and information about the parameters' tolerances. The method uses a VHDL description and is verified on ISCAS85 benchmark circuits. Matlab was used for data processing.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

Study on Signal Integrity Simulation for High Speed Serial Rapid IO

With the increases of signal transmission rate in digital systems, the signal integrity becomes increasingly important in high-speed circuit design. During the hardware design of high-speed serial Rapid IO, signal integrity simulation of 5Gbps high-speed serial bus had been carried out by using Channel Analysis tools. Reliable data was formed by effectively analysis and evaluation of pre-simulation, the signal quality of high-speed serial Rapid IO was verified by post-simulation. The non-ideal design parameters were optimized by referring to the effective data obtained in pre-simulation. Signal quality has been greatly improved by parameters optimization. Signal integrity simulation analysis and verification of serial Rapid IO provides strong support for the design and significantly improves the efficiency of hardware design.

Radiation Effects in SiGe Technology

Silicon-Germanium (SiGe) technology effectively merges the desirable attributes of conventional silicon-based CMOS manufacturing (high integration levels, at high yield and low cost) with the extreme levels of transistor performance attainable in classical III-V heterojunction bipolar transistors (HBTs). SiGe technology joins together on-die high-speed bandgap-engineered SiGe HBTs with conventional Si CMOS to form SiGe BiCMOS technology, including all the requisite RF passive elements and multi-level thick-Al metalization required for high-speed circuit design. Such an silicon-based integrated circuit technology platform presents designers with an ideal division of labor for realizing optimal solutions to many performance-constrained mixed-signal (analog + digital + RF) systems. The unique bandgap-engineered features of SiGe HBTs enable several key merits with respect to operation across a wide variety of so-called “extreme environments”, potentially with little or no process modification, ultimately providing compelling advantages at the circuit and system level, across a wide class of envisioned commercial and defense applications. Here we give an overview of this interesting field, focusing primarily on the intersection of SiGe HBTs, and circuits built from them, with radiation-intense environments such as space.

PNP Transistor Design and Simulation in SiGe BiCMOS with Low Cost and High Performance

The study and design of a low cost and high performance vertical PNP transistor at BiCMOS process platform is presented. The effect of different device designs on baseline process has been compared in terms of their electrics characteristics simulation result. The performance of PNP has been improved further through process optimization with the aid of process simulation. The fabricated PNP transistor silicon data shows consistent performance with simulation. Finally the performance of PNP device has met the target including current gain above 38, breakdown voltage (BV CEO) over 7 volts and cut-off frequency (f T) 10GHz. Its performance addresses the requirement for high speed circuit design.

Heat-Sink Modeling and Design With Dipole Moments Representing IC Excitation

Electromagnetic field coupling and radiation from a heat sink is a challenging issue in the electromagnetic compatibility design of high-speed circuits. In order to accurately predict the fields excited by a heat sink, an approach is proposed in this paper to include the equivalent excitation of the heat sink, which is described by some dipole moments constructed from the near-field scanning of the integrated circuit beneath the heat sink. With both the dipole moments and the passive heat-sink structure incorporated in a full-wave model, near-field coupling and far-field radiation can be estimated, and the heat-sink structure can be optimized for mitigating unintentional interferences. Two examples are used to validate and demonstrate the proposed approach.

Single-Event Analysis and Hardening of Mixed-Signal Circuit Interfaces in High-Speed Communications Devices

High-speed communication systems typically employ a mix of signal types and circuit topologies in order to optimize efficient data propagation. Current-mode logic is the industry standard for high-speed CMOS circuit design due to the inherent speed of current steering. However, current-mode output voltages are not rail-to-rail and therefore require a conversion to a full-swing signal for downstream CMOS logic. This interface between current-mode and CMOS logic is found to be vulnerable to single-event effects. A radiation-hardened-by-design solution is proposed for such interfaces.

Measurement of voltage-dependent capacitance using a TDR system

The measurement of circuit parameters and the evaluation of equivalent circuit models are necessary for noise analysis or high-speed operation circuit design for power electronics circuits. Recently, time domain reflectometry (TDR) has emerged as a technique for measuring circuit parameters. This paper proposes a TDR method for measuring the voltage-dependent capacitance of a power MOSFET. This method can be used to measure the output capacitance Coss of a MOSFET for any DC bias voltage. The Coss of a MOSFET with VDS = 350 V was measured in an experiment, while the datasheet gives values of Coss only for VDS values in the range of 35 to 100 V. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(3): 31-38, 2012; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.21289

TDR Measurement Method for Voltage-Dependent Capacitance of Power Devices and Components

The measurement of circuit parasitic parameters and the evaluation of equivalent circuit models are both necessary techniques for noise analysis and the circuit design of high-speed power electronics circuits. Recently, time-domain reflectometry (TDR) has emerged as a technique for measuring circuit parameters. This paper proposes a TDR method for measuring the voltage- dependent capacitance of power devices and passive components. This method can be used to measure the capacitance on any dc bias voltage. The C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oss</sub> value of MOSFETs with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0-350 V, the anode-cathode capacitance under reverse bias condition on SiC diodes, and voltage-dependent capacitances of ceramic capacitors were measured in experiments.

Multipoint Full-Wave Model Order Reduction for Delayed PEEC Models With Large Delays

The increase of operating frequencies requires 3-D electromagnetic (EM) methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D EM methods and model order reduction (MOR) techniques are used to reduce such a high complexity. When signal waveform rise times decrease and the corresponding frequency content increases, or the geometric dimensions become electrically large, time delays must be included in the modeling. A PEEC formulation, which include delay elements called τ PEEC method, becomes necessary and leads to systems of neutral delayed differential equations (NDDE). The reduction of large NDDE is still a very challenging research topic, especially for electrically large structures, where delays among coupled elements cannot be neglected or easily approximated by rational basis functions. We propose a novel model order technique for τ PEEC models that is able to accurately reduce electrically large systems with large delays. It is based on an adaptive multipoint expansion and MOR of equivalent first-order systems. The neutral delayed differential formulation is preserved in the reduced model. Pertinent numerical examples based on τ PEEC models validate the proposed MOR approach.

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under 2 31 –1 bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 µm CMOS process.

Physics-Based Passivity-Preserving Parameterized Model Order Reduction for PEEC Circuit Analysis

The decrease of integrated circuit feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods, and model order reduction (MOR) methods have proven to be very effective in combating such high complexity. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the circuit under study as a function of design parameters such as geometrical and substrate features. Traditional MOR techniques perform order reduction only with respect to frequency, and therefore the computation of a new electromagnetic model and the corresponding reduced model are needed each time a design parameter is modified, reducing the CPU efficiency. Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters of the circuit, such as geometrical layout or substrate characteristics. We propose a novel PMOR technique applicable to PEEC analysis which is based on a parameterization process of matrices generated by the PEEC method and the projection subspace generated by a passivity-preserving MOR method. The proposed PMOR technique guarantees overall stability and passivity of parameterized reduced order models over a user-defined range of design parameter values. Pertinent numerical examples validate the proposed PMOR approach.

RF CMOS Integrated Circuit: History, Current Status and Future Prospects

As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimeter-wave or terahertz-wave region and achieve high speed and large-capacity data transmission; and (iii) microminiaturized low-power RF communication systems that will be extensively used in our everyday lives. However, classical technology for designing analog RF circuits cannot be used to design circuits for the abovementioned devices since it can be applied only in the case of continuous voltage and continuous time signals; therefore, it is necessary to integrate the design of high-speed digital circuits, which is based on the use of discrete voltages and the discrete time domain, with analog design, in order to both achieve wideband operation and compensate for signal distortions as well as variations in process, power supply voltage, and temperature. Moreover, as it is thought that small integration of the antenna and the interface circuit is indispensable to achieve miniaturized micro RF communication systems, the construction of the integrated design environment with the Micro Electro Mechanical Systems (MEMS) device etc. of the different kind devices becomes more important. In this paper, the history and the current status of the development of RF CMOS circuits are reviewed, and the future status of RF CMOS circuits is predicted.

A Method for Measuring Voltage-Dependent Capacitance Using TDR System

The measurement of circuit parasitic parameters and evaluation of equivalent circuit models are necessary for a noise analysis or a high-speed operation circuit design of power electronics circuits. Recently, time domain reflectmetry (TDR) has emerged as a technique for measuring circuit parameters. This paper proposes a TDR method for measuring the voltage-dependent capacitance of a power MOSFET. This method can be used to measure the output capacitance Coss of a MOSFET for any DC bias voltage. The Coss of a MOSFET with VDS=350 V was measured in an experiment, while the datasheet gives values of Coss only for V DS values in the range 35-100 V.

Guaranteed Passive Parameterized Model Order Reduction of the Partial Element Equivalent Circuit (PEEC) Method

The decrease of IC feature size and the increase of operating frequencies require 3-D electromagnetic methods, such as the partial element equivalent circuit (PEEC) method, for the analysis and design of high-speed circuits. Very large systems of equations are often produced by 3-D electromagnetic methods. During the circuit synthesis of large-scale digital or analog applications, it is important to predict the response of the system under study as a function of design parameters, such as geometrical and substrate features, in addition to frequency (or time). Parameterized model order reduction (PMOR) methods become necessary to reduce large systems of equations with respect to frequency and other design parameters. We propose an innovative PMOR technique applicable to PEEC analysis, which combines traditional passivity-preserving model order reduction methods and positive interpolation schemes. It is able to provide parametric reduced-order models, stable, and passive by construction over a user-defined range of design parameter values. Numerical examples validate the proposed approach.

A Novel Combined Equivalent Networks Analysis for Power and Ground Planes With Narrow Slots

Resonance characteristics of power and ground planes with narrow slots are very important for the electromagnetic compatibility design of high-speed digital circuits. To efficiently and accurately model such resonance characteristics, we propose a novel combined equivalent networks method. By using the modal-decoupling technology, the whole gapped power and ground planes are decoupled into two subdomains: the power and ground planes, and the slots, which support parallel plate mode and slot mode, respectively. After this, efficient integral equations are created on each subdomain. The integration paths are discretized into small segments, on which network ports are defined. In this way, these two subdomains are equivalent to two microwave networks. The impedance and admittance matrices of the equivalent networks are extracted through the moments method solution of the created integral equations. Finally, these two equivalent networks are connected together to consider the mode conversion between the parallel plate mode and slot mode. The proposed method is very efficient for the analysis of power integrity of the gapped power and ground planes. By comparing with available full-wave methods, the accuracy and efficiency of the proposed method are verified.

Clock-tree synthesis for low-EMI design

In modern digital ICs, the increasing demand for performance and throughput requires higher operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip clock signals with fast rise/fall times are among the most detrimental sources of electromagnetic (EM) noise, since not only they generate radiated emissions, but they also have a large impact con the conducted emissions, as the power rail noise localized in close proximity of the toggling clock edges propagates to the board through the power and ground I/O pads. In this work, we analyze the impact of different clock distribution solutions on the spectral content of typical on-chip waveforms, in order to develop an effective methodology for EMC-aware clock-tree synthesis, which globally reduces the EM emissions. Our approach can be seamlessly integrated into a typical design flow, and its effectiveness is demonstrated with experimental results obtained from the clock distribution network of an industrial digital design.