Abstract
The most important feature of modern integrated circuit is the speed. It depends on circuit's delay. For the design of high-speed digital circuits, it is necessary to evaluate delays in the earliest stages of design, thus making it easy to modify and redesign a circuit if it's too slow. This paper gives an approach for efficient delay estimation in the describing phase of the circuit design. The method can statistically estimate the minimum and maximum delay of all possible paths and signal transitions in the circuit, considering the practical implementation of circuits, and information about the parameters' tolerances. The method uses a VHDL description and is verified on ISCAS85 benchmark circuits. Matlab was used for data processing.
Highlights
Korišćenje record tipa signala omogućava signalima da pored logičkog stanje nose još nekoliko informacija, što je ključno za implementaciju metoda [12], [13]
Svako logičko kolo modeluje se zadavanjem sledećih parametara:
Dobijeni broj umanjen za jedan daje pravu vrednost fanout-a posmatranog kola, i on se zatim prepisuje preko inicijalne vrednosti u instanci istog logičkog kola na prvoj poziciji generik mape
Summary
Predloženi metod procenjuje kašnjenja strukturno najkraćih i najdužih puteva signala u kolu. Paralelna propagacija svih mogućih kombinacija ulaznih vektora, a informacija o kašnjenju se akumulira prolaskom kroz svako logičko kolo, sve dok se ne doñe do posmatranog čvora ili izlaza kola [11]. Rezultat ovog procesa su maksimalna i minimalna kašnjenja rastućih i opadajućih ivica signala do svih izlaza u kolu. Informacije o kašnjenjima tranzicija signala simultano se osvežavaju prolaskom kroz svako kolo sve dok se ne stigne do primarnog izlaza kola. Kašnjenje rastuće ivice poslednjeg logičkog kola sa sl. Treba istaći da predloženi metod procenjuje i minimalna kašnjenja svih tranzicija signala u kolu. Korišćenje record tipa signala omogućava signalima da pored logičkog stanje nose još nekoliko informacija, što je ključno za implementaciju metoda [12], [13]
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