Design and Implementation of Low-Power Dynamic Comparator

Abstract

Dynamic comparators are highly utilized in design of high-speed digital circuits. More precisely, Low power and high-speed dynamic comparators are the key elements in manufacturing of CPUs in many electronic devices. These CPUs consist of many comparison circuits known as comparators. This journal paper presents a low voltage thereby a low power Double Tail Dynamic Comparator (DTDC) with relatively less power consumption when compared to existing designs. In this journal paper, various types of dynamic comparators are discussed and compared with the proposed design. Dynamic comparators based on Double Tail technique, floating inverter amplifier technique and regenerative latch technique etc., are compared to the proposed design. This design is simulated using 250nm technology with the aid of Tanner EDA simulation tool. The pre-amplification process in this proposed design is implemented using Self-biasing technique. Self-biasing technique produces low kick back noise during the operation of this proposed design. The simulated results are mentioned below.