High-speed Buffer Research Articles

High-speed voltage buffers for the experimental characterization of CMOS transconductance operational amplifiers

Two voltage buffers realized with discrete components are presented which provide very low input capacitance and input bias current, high-frequency capability and low-output resistance. This performance means they are well suited for employment in the characterization of operational amplifiers and specifically CMOS transconductance operational amplifiers.

Tandem-crosspoint ATM switch with input and output buffers

This letter proposes a high-speed input and output buffering asynchronous transfer mode (ATM) switch, named the tandem-crosspoint (TDXP) switch, The TDXP switch consists of multiple crossbar switch planes, which are connected in tandem at every crosspoint. The TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. In addition, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. It is shown that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput.

Asynchronous phase-modulated optical fiber-ring buffer

We investigate the dynamics of a 5-Gbit/s packet of ones and zeros loaded into a 0.5-kbit, phase-modulated optical fiber-ring buffer. A new mode of operation is explored in which the cavity length of the buffer is slightly detuned from the frequency driving the phase modulator. We examine the conditions for successful packet loading and the packet storage behavior. In addition, relaxation oscillations, which affected the storage time of previous high-speed optical ring buffers, are nearly eliminated with a cw holding beam, and significantly enhanced storage times are obtained.

Performance of ATM switch fabric using cross-point buffers

Multistage switches consisting of a number of stages of small switching elements (SE) are often used in ATM switch fabrics. An ATM switch fabric performs the functions of switching and buffering of cells. The location of buffers inside a fabric is critical in the performance of the switch. Output buffered SEs have a higher throughput than input buffered SEs. Moreover, output buffered SEs do not suffer from buffer hogging as found in shared buffered SEs operating in a nonuniform traffic environment. However, output-buffered SEs require internal speedup, thereby requiring high-speed buffers and complex buffer management hardware. Crosspoint buffering, however, enjoys the advantages of output buffering without requiring an internal speedup of its buffers. The objective of this paper is to study the performance of a crosspoint buffered ATM switch operating under uniform and nonuniform traffic patterns. The performance of the crosspoint buffered switch is compared with that of the output buffered switch. Analytical models based on the Markov chains are developed to facilitate the study. The results from the model are validated using simulation. It is shown that the model provides very accurate results.

YIQ vector quantization in a new color palette architecture

Many CRT displays use color palettes to save highspeed frame buffer memory and to support many interactive, real-time graphics and imaging operations. Existing quantization algorithms for color palettes cluster colors as 3-D vectors in a color space. Thus, they fail to remove the statistical redundancy in the image space. This weakness prevents a more efficient use of frame buffer capacity. We propose a simple product vector quantization (VQ) technique for frame buffers that exploits redundancies in both image and color spaces. The new VQ technique can reduce the frame buffer use of a color image by half from the current algorithms with comparable image quality. The NTSC YIQ rather than RGB color space is used in our product VQ scheme. Consequently, we propose to modify the current architecture of the color palette to suit the proposed product VQ algorithm in the YIQ mode. The modified color palette is nearly ten times smaller than the current RGB palette and is more flexible. The improved space efficiency in both frame buffer and color palette is achieved while neither complicating the control or logic of the frame buffer architecture nor increasing computational complexity of color quantization.

A high-speed BiCMOS tristate buffer

A high-speed BiCMOS tristate buffer with a single bipolar device pull-up structure for driving a large capacitive load is presented. According to SPICE simulation results, the buffer, which occupies about an identical area, has a 2*improvement in delay time as compared to the CMOS tristate buffer. >

Very-high-frequency CMOS analogue buffer

A simple CMOS on-chip differential buffer is presented. From simulations based on a 2 μm n-well CMOS process, this buffer can give a 260 MHz cutoff frequency with a load of 50 kΩ paralleled by 1 pF. THD at 1 MHz for 1 V peak to peak is as low as 0.003%. Offset voltage is only a few millivolts even if considering mismatch among the transistors. The circuit is very useful as a high-speed internal node buffer or test/pin drive buffer. The power supply can be as low as ±2.5 V.

A fast data-bus to buffer-memory interface

A fast, economical VME based interface between fast data buses and high speed buffer memories has been built. This module in addition to handling the hand-shaking lines, supplies a gate, a busy signal, and a clear signal at the end of data transfer. A header word with programmable contents is inserted at the beginning of each event giving a discernable event boundary. This device, dubbed the FERA Faucet Maier (FFM), has been applied to the LeCroy ECLine bus coupled to a Creative Electronics Solution 8170 High Speed Memory. It will transfer data at rates up to 10 Mbytes/s from the LeCroy FERAs to the VME based memory.

Storage hierarchies

The storage hierarchy is a natural structure, given the set of available technologies and their price and performance characteristics. The physical structure of the storage subsystem is described, and the flow of data through the system is traced. The concept of a storage hierarchy is discussed, and the specific components of the IBM storage hierarchy from the processor high-speed buffer (HSB) to the on-line DASD configuration are described in detail. Trade-offs between technologies and the interactions among the levels of the hierarchy are discussed. In particular, the importance of the I/O boundary, processor storage volatility, and data sharing are highlighted. A continuous increase in virtual storage capacity can be seen in the evolution of large-scale operating systems, and MVS/ESA™ now provides the ultimate virtual capacity and function. New virtual structures available in MVS/ESA are discussed, and their relationship to the storage hierarchy is studied. The importance of storage to the performance and cost of a large processing system leads to a discussion of guidelines for storage configuration and data placement within the hierarchy.

A large, high-speed memory buffer for high energy physics data

Abstract Many high-data-rate experiments in elementary particle physics suffer large dead-times due to the slow speeds with which the on-line computer can read in data from each event. To eliminate this bottle-neck, we have designed, constructed, and made extensive use in a physics experiment of a 4 megabyte memory buffer which employs ordinary dynamic RAM memory chips and which accepts all of our event data generated during a beam spill at Fermilab at a rate of 14 Mbyte per second.

Real-time data acquisition system for laser and radio frequency spectroscopy

A low-cost real-time data acquisition system utilising a master (PC-XT) and a slave (Z80) computer for high-resolution atomic spectroscopy is described. The master and the slave computer are linked by a high-speed parallel FIFO buffer permitting data acquisition on a fixed time schedule with 4 mu s time resolution. A modular interface box allows the system to control complex spectroscopic experiments. The use of commercial software packages allows fast and efficient data reduction and analysis on the same computer system. The performance of the system has been demonstrated in polarisation spectroscopy experiment on zirconium.

An Empirical Study of Task Switching Locality in MVS

The "hit ratio" of a high-speed buffer (cache) depends on the "locality" of memory references. However, locality of reference is disturbed and the hit ratio decreases whenever a task switch occurs. This performance degradation can be minimized if "locality of task switching," the tendency for a small set of favored tasks to be frequently executed, exists and the cache is organized in such a way that it can hold blocks (lines) of multiple tasks. Locality of task switching and locality of memory references in individual tasks exhibit overall locality of memory references at a system level. This paper addresses the following questions. Does locality of task switching really exist? How can it be modeled? Task switching in IBM operating system/virtual storage with multiple virtual storage (OS/VS2 MVS) was measured using event traces for three different workloads to show that locality of task switching actually exists in MVS. Two different models of task switching are proposed. These models can be incorporated into cache multitasking models to predict more accurately the misses in real computer systems. A key parameter of these models is the task execution interval; measurements of execution intervals for the workloads used in the paper are presented and discussed.

Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories

A possible design alternative for improving the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers by reducing the effective memory access time, and affect the delays caused by memory conflicts. In this paper, we study the effectiveness of caches in a multiprocessor system. The shared memory is pipelined and interleaved to improve the block transfer rate, and it assumes a two-dimensional organization, previously studied under random and word access. An approximate model is developed to estimate the processor utilization and the speed-up improvement provided by the caches.

Performance of cache-based multiprocessors

A possible design alternative to improve the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers, reducing the memory access time, and affect the delays caused by memory conflicts. In this paper, we study the performance of a multiprocessor system with caches. The shared memory is pipelined and interleaved to improve the block transfer rate, and assumes an L-M organization, previously studied under random word access. An approximate model is developed to estimate the processor utilization and the speedup improvement provided by the caches. These two parameters are essential to a cost-effective design. An example of a design is treated to illustrate the usefulness of this investigation.

Physiological and Real-Time Gating of Data for Positron Emission Computed Tomography

Data for emission computed tomography (ECT) studies is obtained from detector arrays positioned around a subject. In ECT studies dynamic data is taken representing such functions as blood flow, blood pool, cell perfusion and cell metabolism. These may vary with time due to physiological reasons or cyclicly due to bio-mechanical (e.g. cardiac) reasons. Since the time to acquire statistically significant data is typically much longer than the period of these physiological cycles, data must be taken for discrete divisions of many cycles, in synchronism with the physiological process. Physiological gating may be applied, for instance, to ECT studies of the heart. In these studies, the time period of the cardiac cycle is subdivided. Data from each division of the cycle is compiled into a separate image. A single cardiac cycle does not provide enough data at reasonable subject dose rates to compile an image for each division; therefore, data is taken for several cardiac cycles with separate storage for each division. The resulting image for each division will show increased resolution due to minimization of distortion. This technique may also be applied to respiratory and other dynamic processes. An alternate form of gating creates a cycle based on clock time rather than a physiological process. This method allows the use of high speed buffering to increase the rate of data images acquired. This paper presents a method of providing gating based on either physiological processes or clock time.

A 300 V//spl mu/s monolithic voltage follower

An open-loop, JFET input, high-speed buffer, designed without feedback, is described. Careful biasing of source and emitter followers ensures accurate unity gain and gain linearity with 10 mA of load current. A unique quasi-quad input FET layout provides excellent matching and thermal gradient cancellation and simultaneously optimizes speed performance. Offset voltage is permanently adjusted at wafer test by Zener-zap trimming. The output is capable of driving large capacitive loads with 70 mA of peak current.

High-speed buffering for variable length operands

Variable word length processing is valuable for data base manipulations, editing functions in time-sharing systems, input-output data formatting, and vector operations, but current computer architectures seldom provide efficient means for manipulating variable length operands. A specialized computer architecture has been proposed to deal with the problems of variable length byte string processing. Operand buffering is a key part of the proposed architecture because the buffer: (1) replaces registers for variable length operands, (2) resolves address precision and operand boundary problems between the main memory and the ALU, and (3) can provide simultaneous access to several operands for faster execution. General observations are made about requirements which constrain memory buffer design and the merits of four memory buffering schemes are discussed. The most suitable of the buffering schemes is discussed in some detail. This scheme provides a separate cache for each of the operands. Hardware costs and timing considerations are given, and show that the multiple-buffer approach to variable word length buffering provides a reasonable cost-performance solution.

An 8K B random-access memory chip using the one-device FET cell

Describes the design, fabrication, and testing of an 8192-b p-channel fully-functional random access memory. Novel features of this device are discussed. Among these are the following: inversion layer capacitor one-device cell; the use of a high speed buffer to maximize data transfer; and a minimization of cell pitch limitations through the use of a unique word system circuit design. Performance, power, and yields are also discussed.

Semiconductor random-access memories

In the last few years, semiconductor random-access memory (RAM) components have been introduced into high-speed scratchpad applications and small buffer memory systems, where the performance or cost advantage of semiconductor components is greatest. More recently, developments in the technology of large-scale integrated (LSI) circuits have resulted in cost-performance characteristics of semiconductor RAMs that are competitive in computer main-frame memories as well. This article reviews the basic circuit concepts used in these components, representative products that are presently available, and some systems considerations involved in their use.

A Logic-in-Memory Computer

If, as presently projected, the cost of microelectronic arrays in the future will tend to reflect the number of pins on the array rather than the number of gates, the logic-in-memory array is an extremely attractive computer component. Such an array is essentially a microelectronic memory with some combinational logic associated with each storage element. A logic-in-memory computer is described that is organized around a logic-enhanced ``cache'' memory array. Used as a cache, a logic-in-memory array performs as a high-speed buffer between a conventional CPU and a conventional memory. The effect on the computer system of the cache and its control mechanism is to make the main memory appear to have all of the processing capabilities and almost the same performance as the cache. Operations within the array are naturally organized as operations on blocks of data called ``sectors.'' Among the operations that can be performed are arithmetic and logical operations on pairs of elements from two sectors, and a variety of associative search operations on a single sector. For such operations, the main memory of the computer appears to the program to be composed of a collection of logic-in-memory arrays, each the size of a sector. Because of the high-speed, highly parallel sector operations, the logic-in-memory computer points to a new direction for achieving orders of magnitude increase in computer performance. Moreover, since the computer is specifically organized for large-scale integration, the increased performance might be obtained for a comparatively small dollar cost.