High-speed Board Research Articles

10.3125Gbps High-Speed SFP+ Channel Signal Integrity Evaluations

10.3125Gbps interfaces are now extensively used in almost all telecom and datacom applications, and high-speed board interconnection is becoming more and more important to the 10+Gbps channels. In this paper, signal integrity (SI) performance for 10.3125Gbps SFP+ interface were studied with EM simulation, then the simulation results were compared with the lab measurement results. To find optimal SI performance, different output voltage and pre-emphasis taps were tuned, and the crosstalk in the channel was also discussed. Finally, several methods to improve SFP+ SI performance were proposed.

Operating System for the Dynamic Belt Measurement

Firstly, The core model, structure module, performance characteristics and JTAG debug interface of the microprocessor were described by this article. Then, the system power supply module, prior to the passage weighing signal and tachometer signal circuits were designed in this paper. Secondly, according to the operational needs of the belt scale system, the external memory circuit and the TFT-LCD touch screen circuit modules were studied. Finally, the high-speed circuit board PCB designed to solve EMC problems. And it described the data collection and weighing controller bus communication test situation and established the communications test platform of Profibus-DP, introduced the test experimental procedures, experiment shows the communication between master and slave test results are correct.The computing speed and accuracy, data processing compared with traditional electronic belt scale, information exchange, integration, reliability and stability will be greatly improved by the advanced embedded technology and so on.

Escaped Boundary Pins Routing for High-Speed Boards

Routing for high-speed boards is still achieved manually today. There have recently been some related works to solve this problem; however, a more practical problem has not been addressed. Usually, the packages or components are designed with or without the requirement from board designers, and the boundary pins are usually fixed or advised to follow when the board design starts. In this paper, we describe this fixed ordering boundary pin routing problem, and propose a practical approach to solve it. Not only do we provide a way to address, we also further plan the wires in a better way to preserve the precious routing resources in the limited number of layers on the board, and to effectively deal with obstacles. Our approach has different features compared with the conventional shortest-path-based routing paradigm. In addition, we consider length-matching requirements and wire shape resemblance for high-speed signal routes on board. Our results show that we can utilize routing resources very carefully, and can account for the resemblance of nets in the presence of the obstacles. Our approach is workable for board buses as well.

Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards

Shrinking transistor sizes, increasing circuit complexities, and high clock frequencies bring new board-routing challenges that cannot be handled effectively by traditional routing algorithms. Many high-end designs in the industry today require manual routing efforts, which increases the design-cycle times considerably. In this paper, we propose an escape-routing algorithm to route nets within multiple dense components simultaneously so that the number of crossings in the intermediate area is minimized. We also show how to handle high-speed-design constraints within the framework of this algorithm. Experimental comparisons with a recently proposed algorithm show that our algorithm reduces the via requirements of industrial test cases on average by 39%.

Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards

Fast and accurate power bus designer (FAPUD) for multi-layers high-speed digital boards is the power supply network design tool for accurate and precise high speed board. FAPUD is constructed based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching in can be carried out because the I/O switching effect on a power supply noise can estimate for the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

Algorithmic study of single-layer bus routing for high-speed boards

As the clock frequencies used in industrial applications increase, the timing requirements on routing problems become tighter, and current routing tools cannot successfully handle these constraints any more. In this paper, the authors focus on the high-performance single-layer bus routing problem, where the objective is to match the lengths of all nets belonging to each bus. An effective approach to solve this problem is to allocate extra routing resources around short nets during routing, and use those resources for length extension afterwards. First, a provably optimal algorithm for routing nets with minimum-area maximum-length constraints is proposed. Then, this algorithm is extended to the case where minimum constraints are given as exact length bounds, and it is also proven that this algorithm is near-optimal. Both algorithms proposed are shown to be scalable for large circuits, since the respective time complexities are O(A) and O(AlogA), where A is the area of the intermediate region between chips.

Two-layer bus routing for high-speed printed circuit boards

The increasing clock frequencies in high-end industrial circuits bring new routing challenges that cannot be handled by traditional algorithms. An important design automation problem for high-speed boards today is routing nets within tight minimum and maximum length bounds. In this article, we propose an algorithm for routing bus structures between components on two layers such that all length constraints are satisfied. This algorithm handles length extension simultaneously during the actual routing process so that maximum resource utilization is achieved during length extension. Our approach here is to process one track at a time, and choose the best subset of nets to be routed on each track. The algorithm we propose for single-track routing is guaranteed to find the optimal subset of nets together with the optimal solution with length extension on one track. The experimental comparison with a recently proposed technique shows the effectiveness of this algorithm both in terms of solution quality and run-time.

PC를 이용한 소규모 기가비트 VLBI 관측시스템

In this paper, we propose a small-scale Gigabit VLBI observing system for the Korean VLBI Network (KVN) under construction. The system consists of high-speed sampler, IP-VLBI board, PC-VSI board, and software correlator. Radio signal received by receiver is sampled by high-speed sample. at 1 Gsps (Gigabit sample per second) rate with 2 bits quantization. The digitized signal is recorded in PC and the software correlator does the cross correlation. IP-VLBI board will be used for the geodesy VLBI observation, while PC-VSI board is for the astronomical VLBI observation. The PC-VSI board adopts the VSI-H (VLBI Standard Interface Hardware). The proposed system is based on commercial PCs and therefore can be built inexpensively.

Electrical modeling of ball grid array packages based on one-port S-parameter measurement for electrical evaluation of high-speed test board

Abstract To electrically characterize ball grid array (BGA) packages, one-port S -parameter measurements have been performed. Equivalent circuit parameters using the Γ and T models are extracted from measured S -parameters for three different frequency ranges. The accuracy of two selected equivalent circuits is evaluated by comparison between the re-calculated S 11 using the extracted equivalent circuit parameters and measured S -parameters. The results show that the T lumped model can be used to represent S -parameters of BGA packages without distributed elements up to 2 GHz.

Multichannel ultrathin silicon-on-sapphire optical interconnects

Multichannel optical interconnects were developed using vertical-cavity surface-emitting laser (VCSEL) arrays and metal-semiconductor-metal photodetector (PD) arrays and driven by complementary metal-oxide-semiconductor circuits that were fabricated using ultrathin silicon-on-sapphire (SOS) technology. Low-threshold oxide-confined top-emitting VCSEL 8/spl times/8 arrays were designed and fabricated with off-site contact bonding pads. The arrays were flip-chip bonded to driver arrays on sapphire substrates and mounted on high-speed printed-circuit boards as optical transmitter arrays. The laser output was transmitted through the transparent sapphire substrate and coupled to MSM PD arrays and the SOS receiver. This optical interconnect system was demonstrated to operate at a data rate of 1.0 Gb/s per channel with a power consumption of 28 mW for each channel including transmitter and receiver.

最新の高速板紙抄紙機 高抄速で高品質を得るために

最新の高速板紙抄紙機 高抄速で高品質を得るために

Design of ATM circuit emulation service terminal adapter

The asynchronous transfer mode (ATM) Circuit Emulation Service (CES) terminal adapter (TA) is designed for transporting the DS1/E1 tributary in an ATM network. The DS1/E1 tributary are segmented and reassembled by an ATM adaptation layer 1 (AAL1) segmentation and re-assembly (SAR) field programmable gate array (FPGA) in the low-speed circuit board. Synchronous residual time stamp (SRTS) is used to recover the source clock at the receive end. The high-speed board provides a physical layer and ATM layer functions. A cell multiplexer/demultiplexer FPGA, is designed to route cells to each service low-speed boards. The prototype CES-TA is connected to ATM switches and tested for its performance.

Understanding the importance of signal integrity

For today's high-speed boards and ICs, signal-integrity performance is as important to specify as digital functionality or clock speed. Signal-integrity problems, including delays, ringing, crosstalk, and EMI, can be identified through careful use of simulation. Once potential problems have been identified, layout can be constrained to improve performance, and termination strategies can be applied to minimize the impact of signal integrity on the overall performance of a high-speed design. By addressing signal-integrity problems early, a high-performance product can be produced with higher reliability and lower cost.

Static timing analysis of high-speed boards

Static timing analysis, as is well known, is becoming an indispensable tool for the verification of IC designs. Less well-known is its applicability to the design of high-speed printed-circuit boards. Timing is the key to performance in today's designs. Given the soaring clock rates in the components of circuit boards, a faster transmission of signals from one component to another will improve system performance. It is impossible to analyze by hand every important signal path in a layout of any size; but static timing analysis is exhaustive and therefore a convenient method of ensuring that the design meets its timing requirements. Along with the higher clock rates come shorter signal rise times, which exaggerate reflections, distortions, overshoots, undershoots, and other transmission line effects. Static timing analysis systematically includes such effects in the timing verification. Many tools are available for static timing analysis on ICs and circuit boards. But Motive, from the Quad Design Group of Viewlogic Systems, Camarillo, Calif., tackles nearly the complete spectrum of electronic design, from application-specific ICs (ASICs) and field-programmable gate arrays to circuit boards and even systems consisting of daughter boards and backplanes. Motive's modularity-its ability to utilize a model created at one level of a design in the analysis of a higher level of the design-is one of its most useful features.

1 Gbit/s, 32×32 high-speed space-division switching module for broadband ISDN using SST LSIs

A high-speed 32*32 space-division switching module for high-definition TV broadcasting and switching systems is described. It employs a newly developed Si-bipolar SST 8*8 switch LSI, high-speed peripheral ICs and a high-speed impedance-controlled board. The module is capable of a 1.0 Gbit/s signal speed using 1:1 and 1:n connections. >

Calculating the effective pattern rate for high-speed board test applications

A complex interplay of tester specifications can force in-circuit and functional board test systems to operate at less than their specified maximum pattern rates in real-world test applications. The author explores the factors that combine to limit test speed. He develops models for calculating the effective pattern rate based on tester performance data and the characteristics of the VLSI board under test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>