Abstract
The asynchronous transfer mode (ATM) Circuit Emulation Service (CES) terminal adapter (TA) is designed for transporting the DS1/E1 tributary in an ATM network. The DS1/E1 tributary are segmented and reassembled by an ATM adaptation layer 1 (AAL1) segmentation and re-assembly (SAR) field programmable gate array (FPGA) in the low-speed circuit board. Synchronous residual time stamp (SRTS) is used to recover the source clock at the receive end. The high-speed board provides a physical layer and ATM layer functions. A cell multiplexer/demultiplexer FPGA, is designed to route cells to each service low-speed boards. The prototype CES-TA is connected to ATM switches and tested for its performance.
Published Version
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