Static timing analysis of high-speed boards

Abstract

Static timing analysis, as is well known, is becoming an indispensable tool for the verification of IC designs. Less well-known is its applicability to the design of high-speed printed-circuit boards. Timing is the key to performance in today's designs. Given the soaring clock rates in the components of circuit boards, a faster transmission of signals from one component to another will improve system performance. It is impossible to analyze by hand every important signal path in a layout of any size; but static timing analysis is exhaustive and therefore a convenient method of ensuring that the design meets its timing requirements. Along with the higher clock rates come shorter signal rise times, which exaggerate reflections, distortions, overshoots, undershoots, and other transmission line effects. Static timing analysis systematically includes such effects in the timing verification. Many tools are available for static timing analysis on ICs and circuit boards. But Motive, from the Quad Design Group of Viewlogic Systems, Camarillo, Calif., tackles nearly the complete spectrum of electronic design, from application-specific ICs (ASICs) and field-programmable gate arrays to circuit boards and even systems consisting of daughter boards and backplanes. Motive's modularity-its ability to utilize a model created at one level of a design in the analysis of a higher level of the design-is one of its most useful features.