High-resolution Data Converters Research Articles

Progress of the ECHo SDR Readout Hardware for Multiplexed MMCs

The electron capture in ^{163}Holmium (ECHo) experiment seeks to achieve sub-eV sensitivity of the electron neutrino mass through calorimetric decay spectroscopy of ^{163}Ho in large arrays of cryogenic magnetic microcalorimeters (MMCs). Microwave SQUID multiplexing serves to efficiently increase the number of readout channels, thus calorimeters per array and ultimately per cryostat. A corresponding frequency multiplexing room temperature software-defined radio (SDR) system is in development to enable the readout of this increased number of MMCs per cable. The SDR consists of a custom FPGA platform that provides signal generation and analysis capabilities, as well as tailored signal conversion and analog conditioning front end electronics that enable the room-temperature-to-cryogenic interface. Ultimately, the system will read out 400 multiplexer channels with double pixel detectors through a bandwidth of 4 GHz (IEEE C band). As high-resolution data converters are limited in sample rate, the C-band is split into five sub-bands using a two-stage mixing method. In this contribution, a prototype of the heterodyne RF design is presented. It comprises one of the five 800 MHz sub-bands for a target frequency range between 4 and 8 GHz. Furthermore, the second version of the A/D converter stage is presented, capable of generating and digitizing up to five complex basebands using 1 GSs^{-1} converters, the reference clocks and a flux-ramp signal. We will show first results of their single and combined characterization in the lab. The current state of the prototype hardware enables preliminary measurements, only limited in bandwidth and with slightly higher noise. Potential improvements could be derived and will be implemented in the full bandwidth, 5-sub-band RF PCB design.

A Temperature-Compensated Crystal Oscillator With Piecewise Polynomial Varactor Compensation Achieving ±3.75-ppm Inaccuracy From −30°C to 90°C

This brief presents a low-complexity temperature-compensated crystal oscillator (TCXO). The frequency error compensation over temperature is realized by employing the proposed piecewise polynomial varactor (PPV). The PPV operation is determined by a temperature-dependent voltage generator. The temperature compensation is achieved without using an accurate mapping table and high-resolution data converters. In addition, an amplitude-control loop (ACL) is incorporated to maintain a stable XO operation under process, temperature, and supply voltage variations. This brief is fabricated in a 180-nm CMOS process. The frequency inaccuracy of the proposed 40-MHz TCXO is ±3.75 ppm from −30°C to 90 °C. Operating from a 1.8-V supply, the overall current consumption, including the proposed compensation and ACL, is 0.3 mA.

10-GHz Fully Differential Sallen–Key Lowpass Biquad Filters in 55nm SiGe BiCMOS Technology

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations.

Algorithm and VLSI Design for 1-Bit Data Detection in Massive MIMO-OFDM

The use of low-resolution data converters in the radio-frequency (RF) chains of all-digital massive multiple-input multiple-output (MIMO) basestations promises significant reductions in power consumption, hardware costs, and interconnect bandwidth. We propose a quantization-aware data-detection algorithm which mitigates the performance loss of 1-bit quantized massive MIMO orthogonal frequency-division multiplexing (OFDM) systems. Since the system performance heavily depends on the quality of channel estimates, we also develop a nonlinear 1-bit channel estimation algorithm that builds upon the proposed data detection algorithm. We show that the proposed algorithms significantly outperform linear data detectors and channel estimators in terms of bit error rate. For the proposed nonlinear data detection algorithm, we develop a very large scale integration (VLSI) architecture and present implementation results on a Xilinx Virtex-7 field programmable gate array (FPGA). Our implementation results are, to the best of our knowledge, the first for 1-bit massive MU-MIMO-OFDM systems and demonstrate comparable hardware efficiency with respect to state-of-the-art linear data detectors designed for systems with high-resolution data converters, while achieving lower bit error rate.

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

Device mismatch is a key concern for high-resolution data converters. This paper presents a comprehensive study of the error-feedback (EF)-based mismatch error shaping (MES) technique. EF MES overcomes the key challenge of the classic dynamic element matching-based MES whose complexity grows exponentially with the number of bits; however, the prior EF MES comes with the limitations of limited shaping capability and reduced dynamic range. This paper demonstrates how to perform more advanced EF MES for various types of data converters. Moreover, this paper also proposes the use of digital prediction to address the dynamic range loss issue.

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a two-step incremental A/D converter (IADC) which extends the performance of an Nth-order IADC close to that of a (2N-1)th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and it consumes only 10.7 μW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.

Progress in high-speed and high-resolution CMOS data converters

This paper presents an overview of the status of high-speed and high-resolution CMOS data converters. Techniques and achieved performance are compared using power consumption per step of resolution as a key parameter. The effort in optimizing this quality factor is evident, because of urgency of portable system requirements. Trends towards low-power design and bit-stream processing are also considered.

Noise in mixed continuous-time switched-capacitor sigma-delta modulators

It is commonly accepted that oversampling/noise-shaping is the most suitable technique for implementing high-resolution data converters in MOS technologies. Most existing modulators use switched-capacitor (SC) techniques because they provide a highly controllable design. When compared to continuous-time (CT) techniques, SC techniques have two main drawbacks: settling time limitation and thermal noise folding. In this paper the performance of mixed continuous-time/switched-capacitor (CT-SC) and SC modulators is compared by analytically evaluating the thermal and jitter noise contributions. Relationships are derived which define the conditions for designing mixed modulators with lower levels of noise power than their SC counterparts. The main conclusion is that in mixed modulators the thermal noise can be significantly reduced, while the jitter noise could be a severe limit on the realisation of high resolution converters.