High-resolution ADCs Research Articles

The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs

The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs

A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier

A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier

A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC

A foreground calibration is proposed to obtain the real weights in the split capacitor digital-to-analog- converter (CDAC) of a 14-bit 1-MS/s successive-approximation-register (SAR) ADC. Since the non-linearity of high-resolution SAR ADC is mainly caused by the mismatch of capacitors, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By injecting a multi-level dither signal in both the calibration and conversion phases of the calibration scheme, the precision and non-linearity of SAR ADC can be significantly improved. Simulation results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 79.93 dB and 91.21 dB by employing the proposed calibration technique in a 14-bit split-CDAC SAR ADC. Besides, integral non-linearity (INL) achieves 0.22 least-significant bit (LSB).

A power-efficient CMOS image sensor with current-mode 1-bit log-gradient feature extractor for always-on object detection

This paper presents a power-efficient CMOS image sensor (CIS) for always-on object detection by using 1-bit log-gradient feature extraction in analog current domain. Compared with traditional image sensors with high-resolution ADCs, the proposed CIS extracts gradients in ratio form and generates feature maps at 1-bit resolution, which eliminates unnecessary background information and illumination-related data, and reduces the data computation in the later detector. The system containing the proposed CIS and back-end ANN detector is modeled with python and the simulation achieves an accuracy of 93.2 % for person detection. The CIS employs current mode divider and comparator to compute the gradient ratios. An accurate and configurable muti-input and muti-output (MIMO) current divider is proposed, composed of two cascaded modified second generation current controlled conveyors (M-CCCIIs). The proposed CIS was fabricated in a 0.18 μm standard CMOS process and realized a frame rate of 170 fps and an energy efficiency of 337 pJ/pixel in a power consumption of 1.1 mW. Experimental results show that the proposed CIS can realize the function of extracting log-gradients.

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380–16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 μW while operating at sampling frequency of 500 MS s–1 at supply voltage of 1 V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

A 12~14-Bit SAR-SS Hybrid ADC with SS Bit Shifting Resolution Reconfigurable Method for Bio-Signal Processing

This paper presents a low-power, high-resolution reconfigurable hybrid ADC for bio-electrical signal processing. The proposed ADC contains a SAR ADC for the most significant bit (MSB) and a single-slope ADC for the least significant bit (LSB). To solve the issue of exponentially increasing sampling speed based on the resolution of the single-slope ADC, the SAR ADC is designed to be reconfigurable with a resolution of 8–10-bit, while the single-slope ADC is configured with a resolution of 4-bit. To achieve this resolution reconfiguration, the bit shifting method is proposed and implemented with reconfigurable SAR logic circuit and 4-bit single-slope digital ramp generator. Measurement results demonstrate the power consumption of 34.0 uW, which includes analog power of 23.8 uW and digital power of 10.2 uW, INL/DNL of ±3.5 LSB and −1.0/+2.5 LSB. The ENOB and FoM are measured to be 10.8 bits and 53 fJ/step, respectively.

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

DAC mismatch is a major challenge for high-resolution ADCs. This paper proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm and consumes 0.656 μW under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.

ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application

Computing-in-memory (CIM) relieves the Von Neumann bottleneck by storing the weights of neural networks in memory arrays. However, two challenges still exist, hindering the efficient acceleration of convolutional neural networks (CNN) in artificial intelligence (AI) edge devices. Firstly, the activations for sliding window (SW) operations in CNN still bring high memory access pressure. This can be alleviated by increasing the SW parallelism, but simple array replication suffers from poor array utilization and large peripheral circuits overhead. Secondly, the partial sums from individual CIM arrays, which are usually accumulated to obtain the final sum, introduce large latency due to enormous shift-and-add operations. Moreover, high-resolution ADCs are also needed to reduce the quantization error of partial sums, further increasing the hardware costs. In this paper, a hardware-efficient CIM accelerator, ARBiS, is proposed with improved activation reusability and bit-scalable matrix-vector-multiplication (MVM) for CNN acceleration in AI edge applications. The cyclic-shift weight duplication exploits a third dimension of receptive field (RF) depth for SW weight mapping to reduce the memory accesses of activations, improving the array utilization. The parasitic-capacitance charge sharing is employed to realize high-precision analog MVM in order to reduce the ADC cost. Compared with conventional architectures, ARBiS with parallel processing of 9 SW operations achieves 56.6%~58.8% alleviation of memory access pressure. Meanwhile, ARBiS configured with 8-bit ADCs saves 92.53%~94.53% ADC energy consumption. An ARBiS accelerator is evaluated to realize a computational efficiency (CE) of 10.28 (10.43) TOPS/mm2, an energy efficiency (EE) of 91.19 (112.36) TOPS/W with 8-bit (4-bit) ADCs, achieving <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.4\sim 11.7\times $ </tex-math></inline-formula> ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.6\sim 11.8\times $ </tex-math></inline-formula> ), <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1\sim 3.3\times $ </tex-math></inline-formula> ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4\sim 4\times $ </tex-math></inline-formula> ) improvements over state-of-the-art works, respectively.

АНАЛІЗ АРХІТЕКТУРИ АЦП ПОРОЗРЯДНОГО ВРІВНОВАЖЕННЯ ТА ПІДХОДІВ ДО ЇЇ ВДОСКОНАЛЕННЯ

Successive approximation register analog-digital converters (SAR ADC) represent the majority of the ADC market for medium- to high-resolution ADCs. Modern SAR ADCs allow to ensure a sampling frequency of more than 100 MHz with a resolution of 10 to 12 bits. Features of the ADC architecture of this type: simplicity, high energy efficiency and dependency of conversion time from resolution. The two main components of a SAR ADC that affect its basic characteristics are the comparator and the digital-to-analog converter (DAC). The DAC based on a capacitor matrix is most often used. In practice, when implementing an ADC in an integrated view, when increasing the resolution, the natural increase of the chip area crystals, increase of the energy, which is consumed during the transformation, and decrease in productivity is intensified by number of technical and technological factors The work analyzes a number of modern approaches that are used to improve the characteristics of the SAR ADC in increased resolution. In particular, the segmentation of the DAC capacitor matrix or the division of the capacitor matrix into a matrix of binary weighted capacitors and a matrix of C-2C capacitors allows to reduce the range of required values of capacitor capacities and reduce the total capacity of the matrix. Due to this, in comparison with the basic architecture, when the ADC bit rate is increased, a smaller area on the crystal is required for the implementation of the matrix and higher performance is ensured. Replacing the capacitor of the most significant discharge of the matrix with an exact copy of its other part allows to reduce the energy consumed from the reference voltage source and spent on redistributing the charge between the capacitors of the matrix during conversion.

A low‐cost digital calibration scheme for high‐resolution SAR ADC using Adaptive‐LMS

This paper presents a novel low-cost digital calibration scheme using Adaptive-LMS for high-resolution SAR ADCs. This proposed Adaptive-LMS is realized by perturbing adaptive analog offset and skipping several LSBs' calibration. Compared with a digital calibration scheme based on conventional LMS, the design saves not only die cost but also testing cost (less testing time). During the testing process, the proposed method requires only 16,000 samples to calibrate the capacitor mismatch and the SNDR is improved from 54.1 dB to 68.1 dB for a 12-bit SAR ADC.

Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier

This article presents a delta–sigma modulator (DSM) using a cascoded floating-inverter-based dynamic amplifier. The proposed cascoded dynamic amplifier achieves more than 50-dB dc gain while maintaining an HD3 of better than –110 dBc for signal swings less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300~\mathrm {mV_{ppd}}$ </tex-math></inline-formula> . Compared to the previously reported two-stage floating inverter amplifier (FIA), the cascoded FIA has a lower and a process invariant input-referred noise, making it an ideal choice for high-resolution ADCs. We also show that, when such a single-stage dynamic amplifier, which has a time-varying transconductance, is used in closed-loop switched-capacitor circuits, the settling bandwidth depends on the average transconductance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m,\rm avg}$ </tex-math></inline-formula> during the settling interval. A detailed analysis reveals that, when the floating inverter structure operates in weak inversion for most of the time (which is the power-efficient way to bias the amplifier), this average transconductance depends strongly on the reservoir capacitance value and only weakly on the transistor dimensions. Besides, it is less sensitive to temperature variations, unlike the transconductance of a conventional OTA biased in weak inversion. We also quantitatively derive and show that the cascoded FIA is more power-efficient than a conventional static-current biased operational transconductance amplifier. Using the cascoded FIA, a discrete-time DSM has been designed and fabricated in a 180-nm CMOS process. The modulator runs at 3.072 MHz while consuming 189 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> from a 1.8-V supply. In a bandwidth of 24 kHz, the measured SNR/SNDR/SFDR is 96.4/96.2/114 dB, respectively.

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC

This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.

The AC amplitude and channel characterization of high-resolution digitizers

High-resolution (24-bit) ADC based sampling devices e.g. NI PXI 5922 and NI PXI 4461 are usually used for precise electric power measurement purpose so it is required to characterize them in a proper way. According to that, several measurement techniques are proposed to characterize ac amplitude and channel characteristics at the maximum frequency of up to 100 kHz. An automated test and calibration system based on a planar multijunction thermal voltage converter and a modular electronic instrumentation platform has been developed. Furthermore, two ADCs, i.e. NI PXI 5922 and NI PXI 4461 have been compared with reference standard (Swerlein algorithm) to investigate their precision in RMS amplitude measurement of ac signals. In addition, this paper presents the PXI digitizers’ channel characterization in both sinusoidal and non-sinusoidal regime as the main contribution which results in comprehensive insight into digitizers’ performances and their mutual comparison. Accordingly, relevant uncertainty analysis is presented as well.

A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs

This paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration, internal supply bootstrapping nor resistors. A complete design methodology from architecture to CMOS circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, a 50-kHz ΔΣM IP mapping example in 1.8-V 180-nm CMOS technology is presented with experimental SNDRmax>85 dB and FOMS> 160 dB while dissipating 1.4 mW.

Realization of a variable resolution modified semiflash ADC based on bit segmentation scheme

A modified variable resolution semiflash ADC, based on ?bit segmentation scheme?, is presented. Its speed and comparator count are identical to a normal flash ADC. An 8-bit ADC has 256 different bit combinations. Sixteen consecutive bit combinations from the MSB side - beginning with the first one, remain unaltered for such an ADC. It continues this way till the last group of sixteen bits. In the designed circuit, the four MSB and four LSB bits are determined in the first and second part of the clock. Following the same logic, the bits in a 16-bit ADC can be found out in only two clock cycles by employing only fifteen comparators. It implies that a higher resolution ADC can easily be determined with low power and small die area. It is tested in P-SIM Professional 9 for an 8-bit ADC and curves drawn to establish the validity of the proposal.

All-digital successive approximation TDC in time-mode signal processing

The need for low-power high-resolution ADCs in a broad range of emerging applications and the architecture to realize these ADCs are examined. The pros and cons of various TDC architectures namely flash TDC, Vernier TDC, ΔΣ TDC, and SAR TDC are compared and their suitability for implementing hybrid ADCs to achieve low power and high resolution is investigated. An 8-bit time-mode SAR TDC targeting hybrid ADCs is proposed. The proposed SAR TDC uses a pair of 16-stage pre-skewed delay lines with 16-level digital time interpolation to achieve the targeted resolution and desired power efficiency. The impact of the degree of pre-skewing on both resolution and power consumption is investigated. The nonlinearity of the pre-skewed delay lines is also investigated, along with the impact of PVT uncertainty. The nonlinearity of the digital time interpolators and the impact of PVT uncertainty on time interpolators are also studied. Factors affecting the linearity of digital time interpolators including input-output isolation and input slope are investigated. A detailed treatment of the timing errors arising from device noise and mismatch is provided. The SAR TDC is designed in a TSMC 65 nm 1.0 V CMOS technology and analyzed using Spectre with BSIM3.3 device models. Simulation results show the SAR TDC operated at 10 MS/s achieves 0.33 ps resolution, 84.8 ps measurement range, 7-bits ENOB, and 1.30 pJ/conversion power efficiency.

A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using Ring Amplifier Based Integrators

This brief presents a high-resolution ADC which makes use of the pseudo-pseudo-differential noise filtering technique in an oversampling ADC architecture with ring amplifier based integrators. The pseudo-pseudo-differential noise filtering technique utilizes single-ended circuits while maintaining the even-order rejection found in fully-differential structures which alleviates, in the active analog blocks, the need for differential matching and circuit overhead such as common-mode feedback. Additionally, pseudo-pseudo-differential provides a cancellation of low frequency flicker noise without the need for traditional techniques such as auto-zero, correlated-double-sampling, or chopping and mitigates double-sampling thermal noise penalties by processing input signal twice. In this prototype, the flicker corner is maintained below 50Hz with measured ADC performance achieving a peak SNDR of 105.0dB and a dynamic range of 106.5dB while consuming 1.17mW from a 1.8V supply.

A Wide Dynamic Range Multi-Sensor ROIC for Portable Environmental Monitoring Systems With Two-Step Self-Optimization Schemes

This article presents a wide-dynamic-range multi-sensor readout interface for portable environmental monitoring systems with two-step self-optimization schemes. It proposes two-step self-optimization methods of adaptive range detection and coarse self-cancelation (CSC) for current-type sensor interfaces, and range-based path control and current DAC-based correlated double sampling (CDS) for resistive sensing interfaces. Their digital conversions are provided by two kinds of high-resolution ADCs, namely, an incremental ΔΣ current detector and a two-step SAR- ΔΣ ADC. The proposed ROIC prototype is fabricated in a 180-nm CMOS process, achieving a dynamic range (DR) of 136.5 dB and 160.9 dB, and a maximum SNR of 109.8 dB and 108.6 dB for current and resistance detection, respectively. For system-level feasibility, an environmental monitoring system prototype based on the ROIC is also manufactured and functionally verified by integrating two kinds of in-house micro-electro-mechanical systems (MEMS) sensor devices, the MCU, and the Bluetooth module, supporting wireless air quality and water pollution monitoring capabilities.

Design of high precision transient waveform measurement algorithm based on oversampling and mean filtering

In the transient impulse test of simulated lightning, the accuracy and reliability of digital impulse measurement secondary system has always been a research hotspot in industry and academia. In this paper, an oversampling mean filtering algorithm is proposed to overcome the disadvantages of high-resolution ADC and low-resolution ADC which are greatly affected by quantization noise in the secondary system of impact test measurement. By increasing the sampling frequency and mean filtering, this method can achieve the accuracy index that can only be obtained by expensive high-resolution chip using cheap low-resolution chip, and it is easy to implement. In this paper, the principle of the algorithm is analyzed in detail, and its implementation is described. On this basis, the performance of the algorithm is discussed through simulation analysis, and the effectiveness of the algorithm is verified through experiments.