High-resolution ADCs Research Articles

Low Cost Rotor Fault Detection System for Inverter Driven Induction Motor

In this paper, the induction motor rotor fault diagnosis system using current signals, which are measured using axis-transformation method, and speed, which is estimated using current information, are presented. In inverter-fed motor drives unlike line-driven motor drives the stator currents have numerous harmonics components and therefore fault diagnosis using stator currents is very difficult. The current and speed signal for rotor fault diagnosis needs to be precise. Also, high resolution information, which means the diagnosis system, demands additional hardware such as low pass filter, high resolution ADC, encoder and etc. Therefore, the proposed axis-transformation and speed estimation method are expected to contribute to low cost fault diagnosis systems in inverter-fed motor drives without the need for an encoder and any additional hardware. In order to confirm validity of the developed algorithms, various experiments for rotor faults are tested and the line current spectrum of each faulty situation using Park transformation and speed estimation method are compared with the results obtained from fast Fourier transforms.

A channelized digital receiver design for UWB systems in a multi-path indoor environment

Due to the very wide bandwidth of UWB system, it is hard if not impossible to design high speed and high resolution ADCs with today's technology. This problem can be solved if the received UWB signal is split into a number of subbands by power splitters, analog low-pass filters, mixers and digital filters. By doing this, each of subbands can be sampled at a fraction of effective sampling frequency. In this paper, we present a simpler channelized receiver architecture for UWB systems than previously published work. Moreover, we present a new, though more complex, channelized receiver design for UWB systems in a multipath propagation environment. We also show through simulation that this new receiver achieves very good BER performance.

Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC

A new digital calibration scheme for a 14 bit binary weighted current-steering digital-to-analog converter (DAC) is presented. This scheme uses a simple current comparator for the current measurement instead of a high-resolution ADC. Therefore, a faster calibration cycle and smaller additional circuits are possible compared to the scheme with the high-resolution ADC. In the proposed calibration scheme, the lowest 8 bit part of the DAC is used for both error correction and normal operation. Therefore, the extra DACs required for calibration are only a 3 bit DAC and a 6 bit DAC. Nevertheless, a large calibration range is achieved. Full 14 bit resolution is achieved with a small chip-area. The simulation results show that DNL and INL after calibration are 0.26 LSB and 0.46 LSB, respectively. They also show that the spurious free dynamic range is 83 dB (57 dB) for signals of 24 kHz (98 MHz) at 200 Msps update rate.

A new method for integrating analog to digital conversion based on error reduction

This paper presents a method for eliminating errors of electronic components in integrating analog to digital converters. Offset error in integrator, comparator and amplifiers of dual-slope converter is a great limitation for increasing the resolution of this type of analog to digital converter. The paper proposes an idea that effectively eliminates offset error of integrator and reduces errors of other components. To validate the efficiency of the proposed method, simulation and experimental results are represented in this paper. As a result, this method can potentially allow a cost-effective design of high-resolution ADCs with low performance Op-Amps.

A time efficient method for determination of static non-linearities of high-speed high-resolution ADCs

Static non-linearity tests on ADCs take many hours to complete, especially when they are of high-resolution, say, 10-bits or more. Efforts to reduce this test time have been attempted, but suggested methods are either not suitable for high-speed high-resolution ADCs or deviate from procedures given in relevant standards, viz. IEC 61083-1, IEEE 1057 or IEEE 1241. In this paper, a novel method is proposed to test such ADCs. It is simple, easy to implement, requires less time and does not impose any change to relevant standards. Instead of the conventional method of applying one DC waveform at a time to the ADC, the proposed method involves application of several DC waveforms (say, 32 or 64) at once, configured as a staircase waveform. Many staircases are used to cover the input voltage range. Thus, in a single acquisition, information corresponding to several DC waveform applications is generated. Hence, a reduction in test time is achieved. Generation of these staircases is straightforward using an arbitrary waveform generator. The timesavings achieved from this method depend on available memory and waveform uploading speed of the arbitrary waveform generator.

Digitalization of highly precise fluxgate magnetometers

This paper describes the theory behind all three known ways of digitalizing the fluxgate magnetometers: analogue magnetometers with digitalized output using high resolution ADC, application of the delta–sigma modulation to the sensor feedback loop and fully digital signal detection. At present time the Δ–Σ ADCs are mostly used for the digitalization of the highly precise fluxgate magnetometers. The relevant part of the paper demonstrates some pitfalls of their application studied during the design of the magnetometer for the new Czech scientific satellite MIMOSA. The part discussing the application of the Δ–Σ modulation to the sensor feedback loop theoretically derives the main advantage of this method—increasing of the modulation order and shows its real potential compared to the analog magnetometer with consequential digitalization. The comparison is realized on the modular magnetometer allowing configurations with modulator inside and outside the feedback loop. The last principle is demonstrated on the project of the fully digital fluxgate magnetometer based on the digital signal processor (DSP). The results of the presented projects are compared with recently published competitive projects. The main objective of the paper is then to discuss the potential, real advantages and weakness of each concept and to examine their convenience for future implementations.

Systematic design and modelling of high-resolution, high-speed pipeline ADCs

This paper describes a suitable mathematical model for the design of high-speed, high-resolution pipeline ADCs. The effect of capacitor mismatch and finite amplifier bandwidth and gain on the converter INL and DNL are accurately modelled. On the basis of this model a design optimisation method is provided.

Application of digital sampling techniques to a “single chip telescope” for isotopic particle identification

Some applications of digital sampling techniques are presented which can simplify experiments involving sub–nanosecond timing determinations and energy measurements with nuclear detectors used for Pulse Shape Analysis and Time of Flight measurements in heavy ion experiments. The basic principles of the method are discussed as well as the main parameters that influence the accuracy of the measurements. The method allows to obtain both high resolution time and amplitude information with an electronic chain simply consisting of a charge preamplifier and a fast high resolution ADC (in the present application: 100 MSample/s, 12 bit) coupled to an efficient on-line software: for example the timing resolution can be as good as 100 ps FWHM. Examples of this technique applied to various detectors in heavy-ion experiments involving particle identification via Pulse Shape Analysis (PSA) are presented. Particular attention is devoted to the analysis of the performance of a “Single Chip Telescope” detector coupled to such a sampling system.

Time measurements by means of digital sampling techniques: a study case of [formula omitted] FWHM time resolution with a [formula omitted], [formula omitted] digitizer

An application of digital sampling techniques is presented which can simplify experiments involving sub-nanosecond time-mark determinations and energy measurements with nuclear detectors, used for Pulse Shape Analysis and Time of Flight measurements in heavy ion experiments. The basic principles of the method are discussed as well as the main parameters that influence the accuracy of the measurements. The method allows to obtain both time and amplitude information with an electronic chain simply consisting of a charge preamplifier and a fast high resolution ADC (in the present application: 100 MSample/s , 12 bit ) coupled to an efficient on-line software. In particular an accurate Time of Flight information can be obtained by mixing a beam related time signal with the output of the preamplifier. Examples of this technique applied to Silicon detectors in heavy-ions experiments involving particle identification via Pulse Shape analysis and Time of Flight measurements are presented. The system is suited for applications to large detector arrays and to different kinds of detectors.

A 14-b 20-Msamples/s CMOS pipelined ADC

The performance of high-resolution pipelined ADCs is limited by the residue amplifier gain and settling accuracy. In typical implementations, error sources are capacitor ratio mismatch, op-amp gain, and residue settling. All these affect ADC performance adversely, specifically in high-speed ADCs. Capacitor matching improves as capacitor size increases, but the trend is towards shrinking capacitor size for high-speed conversion. Many innovations to overcome this such as ratio-independent techniques are reported. Among them, capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors. In this work, the one extra clock phase is used advantageously for comparison.

High resolution ADC using phase modulation-demodulation architecture

We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-channel race arbiter and integrated bit-pipelined decimation filter, an interface electronics block converting the ADC output to standard ECL form at sampling rates up to 200 MHz, and a computerized test station performing data acquisition, processing and display in real time. We have demonstrated a fully functional 14-bit ADC chip with 2-channel race arbiter and 16-bit decimation filter with 1:64 decimation ratio operating at 11.2 GS/s. By using additional decimation filtering of the ADC output at room temperature we demonstrated its dynamic programmability and resolution-bandwidth tradeoff. The measured ADC performance (on effective bits) was competitive with the best semiconductor high-resolution ADCs.

High resolution ADC system

We have developed and verified experimentally a novel high-resolution superconducting ADC architecture based on phase modulation/demodulation principle and implemented in RSFQ logic. We have demonstrated an ADC chip providing full implementation of this architecture, including on-chip decimation filter and multiple-channel synchronizer. We have also developed a digital ADC evaluation system consisting of an interface electronics block converting the low-voltage ADC output to standard TTL form at multi-MHz sampling rate, and a computerized test station performing data acquisition, processing and display in real time. Using this system we have demonstrated that for low-frequency (kHz) signals our ADC chips possess linearity in excess of 16 bits with Spur-Free Dynamic Range over 108 dB, which is an important benchmark for any high-resolution ADC technology.

A 12-b, 60-MSample/s cascaded folding and interpolating ADC

The architecture of this 12 b ADC is based on a three-stage conversion, using cascaded folding and interpolating techniques. Compared to other multi-stage ADC architectures, folding and interpolating ADCs are based on non-linear analog pre-processing. This architecture is an attractive solution for high-resolution ADCs, as extremely linear circuit topologies are not required. To increase the resolution of folding and interpolating ADCs above the published 8 b examples, without raising the number of parallel input stages or the number of comparators in the fine-comparator, a cascaded folding and interpolating architecture is introduced. The ADC achieves 64 dB signal-to-noise ratio (SNR) and 75 dB spurious-free dynamic range (SFDR), while quantizing a 15 MHz full-scale input signal at 50 MSample/s. The 7.0 mm/sup 2/ ADC is fabricated in a 13 GHz, 1 /spl mu/m BiCMOS process and dissipates 300 mW from a single 5.0 V supply. The device is mounted in a standard 44-pin plastic package.

A 12-b, 10-MHz, 250-mW CMOS A/D converter

In high-speed and high-resolution ADCs, self-calibration techniques have widely been used to improve linearities by subtracting ADC nonlinear errors in digital domain. However, stand-alone self-calibrated ADC systems employing a CMOS process have not been fully integrated on a single chip. This fully-differential 12 b 4-stage pipelined CMOS ADC uses a modified digital-domain nonlinear error calibration technique. All functional blocks including digital calibration logic, 16 B memory, and bias circuits are fully integrated on a single chip. The ADC is optimized to improve linearity and yield and uses a mid-rise coding technique that is more efficient in using identical circuit blocks repeatedly than a conventional mid-tread coding. As a result, a modular circuit design approach is applied to the proposed ADC, easily modified for 10 b or 14 b resolution by eliminating or adding an identical stage.

High resolution ADC through an IBM parallel printer port

High resolution ADC through an IBM parallel printer port

A CAMAC timing module for the use with high energy resolution detectors

A CAMAC module which measures event times with a resolution of 10 ns continuously over a period of 32.6 days has been built. The event times are stored in a deep buffer memory in form of 48-bit data words. The pulse amplitude of each event can be measured concurrently in a high resolution ADC and stored in another FIFO buffer memory. These amplitudes are tagged with a flag to correlate time with amplitude value unambiguously. In spite of the high operating frequency of 100 MHz necessitating the use of ECL counters, the module is compact (single-width) thanks to the use of TTL registers for the intermediate storage of the 48-bit time-word. The setup and testing of the modules with a NaI-pair spectrometer used in the GALLEX solar neutrino experiment is described. Other possible applications of the module in the field of non-accelerator particle physics are also mentioned.

Reliability of code density test for high resolution ADCs

The effect of convertor internal noise on its output code histogram is analysed. Simulations show that large linearity errors, including missing codes, may vanish when sufficient noise is experienced. Consequently, the code density test is likely to yield a differential nonlinearity error within +/-0.5 LSB for any high accuracy noisy convertor.

A CAMAC System Controlled by an IBM at Computer for Time-Resolved Spectroscopy

An IBM AT computer interfaced to a small CAMAC system offers considerable power without the complexity and expense of a large general-purpose system. Our system for time-resolved spectroscopy features menu-driven FORTRAN-based software; high-resolution and high-speed (8K channels, 5-μs fixed dead time) ADCs; segmentable histogram memories (24-bit counts) with large memory space for many histogram segments; independently variable separate histogram dwell times; remote control via a CAMAC serial highway; and ground isolation between the data acquisition equipment and control computer by means of fiber optics.

A new method for fast analog-to-digital conversion

This paper describes a conversion method for high speed and high resolution ADCs. It may be named a linear discharge method with variable analog offset.

A fast high resolution ADC based on the flash type with a special error correcting technique

A fast 12 bits ADC based on the flash type with a simple special error correcting technique which can effectively compensate the level drift of the discriminators and the droop of the stretcher voltage is described. The DNL is comparable with the Wilkinson's ADC and long term drift is far better than its.