High-resistivity Silicon Substrate Research Articles

Copper pillar interconnect capability for mmwave applications in 3D integration technology

► Dedicated test vehicle is designed to evaluate losses up to 40 GHz of GSG copper μbump transition. ► Capillary underfill and pitch seems to have a weak influence. ► Cu μbump interconnection is the minor RF losses contributor of all interconnects in silicon platform. ► High aspect ratio die assembly with 10 × 3mm 2 dimensions has been assessed and validated. 3D integration technology opens the way of heterogeneous silicon platform, as for example, millimeter-wave functionalities could be integrated in future communication modules. Consequently, copper pillar technology realized at 1st level of interconnection between silicon top dies and silicon interposer must be evaluated in this new frequency range. In this paper, a test vehicle has been designed to assess radio frequency behavior of 3D stacking as insertion losses (IL) up to 40 GHz induce by copper pillar interconnection and assembly parameters (pitch, underfilling, …). Copper pillar ground-signal-ground (GSG) vertical transition exhibits IL lower than 0.2 dB at 40 GHz on high resistive silicon substrate and seems to be the minor contributor of all 3D interconnections as TSV, and RDL. Capillary underfill and GSG transition pitch have been evaluated to have a weak impact. Cu ring designed to limit bleed-out and fillet assures PAD integrity and induces a strong signal reflection above 15 GHz. Finally, process assembly robustness of high aspect ratio top die (10 × 3 mm 2 ) has been assessed with DC measurements.

AlGaN/GaN HEMTs on Silicon Substrate With 206-GHz $F_{ \rm MAX}$

This letter reports on AlGaN/GaN high-electron-mobility transistors (HEMTs) on high-resistive silicon substrate with a record maximum oscillation cutoff frequency FMAX. Double-T-shaped gates are associated with an optimized technology to enable high-efficiency 2-D electron gas control while mitigating the parasitic resistances. Good results ogate-length HEMTf FMAX = 206 GHz and FT = 100 GHz are obtained for a 90-nm gate-length HEMT with 0.25-μm source-to-gate spacing. The associated peak extrinsic transconductance value is as high as 440 mS·mm-1. To the authors' knowledge, the obtained FMAX and Gmext are the highest reported values for GaN HEMTs technology on silicon substrate. The accuracy of the cutoff frequency values is checked by small-signal modeling based on extracted S-parameters.

Novel Low-Loss Photodefined Electrical TSVs for Silicon Interposers

Silicon interposers with through-silicon vias (TSVs) have been widely explored to connect multiple chips using high-density fine-pitch lateral interconnects. However, there are challenges with the TSVs in silicon interposers: (1) TSV losses increase as TSV height increases and are much higher in low-resistivity silicon substrates, which are more economical, than in high-resistivity silicon substrates, and (2) coefficient of thermal expansion (CTE) mismatch between the copper and silicon leads to stress generation. To address this set of challenges, we fabricated and characterized two novel photodefined TSVs for silicon interposers: polymer-clad TSVs and polymer-embedded vias. The fabricated polymer-clad TSVs consist of a ~20 μm thick photodefined dielectric liner instead of a 1 μm thin SiO2 liner, while the polymer-embedded vias consist of copper vias embedded in photodefined polymer wells within the silicon wafer. Compared to the conventional TSVs with thin (~1 μm) SiO2 liner, ~3.5X and ~20X reductions in TSV insertion loss can be obtained at 25 GHz using the fabricated polymer-clad TSVs and polymer-embedded vias, respectively. Full-wave EM simulations were performed in HFSS to compare the insertion loss of the novel TSVs with the conventional TSVs. With respect to the polymer-clad TSVs, in addition to the reduction in TSV insertion loss, a possible reduction in TSV stresses can be obtained using a low Young's modulus material for the thick liner. Finite-element modeling (FEM) simulations were performed in ANSYS to analyze the possible stress reduction that can be obtained using the fabricated polymer-clad TSVs compared to the conventional TSVs. Finally, four-point resistance measurements were performed for the novel TSVs to prove their high yield. In summary, this presentation will report fabrication and resistance measurements of the novel polymer-clad TSVs and polymer-embedded vias as well as HFSS and ANSYS simulations for the novel TSVs.

Terahertz time-domain spectroscopic ellipsometry: instrumentation and calibration

We present a new instrumentation and calibration procedure for terahertz time-domain spectroscopic ellipsometry (THz-TDSE) that is a newly established characterization technique. The experimental setup is capable of providing arbitrary angle of incidence in the range of 15°-85° in the reflection geometry, and with no need for realignment. The setup is also configurable easily into transmission geometry. For this setup, we successfully used hollow core photonic band gap fiber with no pre-chirping in order to deliver a femtosecond laser into a THz photoconductive antenna detector, which is the first demonstration of this kind. The proposed calibration scheme can compensate for the non-ideality of the polarization response of the THz photoconductive antenna detector as well as that of wire grid polarizers used in the setup. In the calibration scheme, the ellipsometric parameters are obtained through a regression algorithm which we have adapted from the conventional regression calibration method developed for rotating element optical ellipsometers, and used here for the first time for THz-TDSE. As a proof-of-principle demonstration, results are presented for a high resistivity silicon substrate as well as an opaque Si substrate with a high phosphorus concentration. We also demonstrate the capacity to measure a few micron thick grown thermal oxide on top of Si. Each sample was characterized by THz-TDSE in reflection geometry with different angle of incidence.

RF MEMS ohmic switches for matrix configurations

Two different topologies of radio frequency micro-electro-mechanical system (RF MEMS) series ohmic switches (cantilever and clamped–clamped beams) in coplanar waveguide (CPW) configuration have been characterized by means of DC, environmental, and RF measurements. In particular, on-wafer checks have been followed by RF test after vibration, thermal shocks, and temperature cycles. The devices have been manufactured on high resistivity silicon substrates, as building blocks to be implemented in different single-pole 4-throw (SP4 T), double-pole double-throw (DPDT) configurations, and then integrated in Low Temperature Co-fired Ceramics (LTCC) technology for the realization of large-order Clos 3D networks.

A 15–50-GHz Quasi-Optical Scalar Network Analyzer Scalable to Terahertz Frequencies

A 15-50-GHz two-port quasi-optical scalar network analyzer consisting of a transmitter and receiver built in a planar technology is presented. The network analyzer is based on a Schottky-diode multiplier and mixer integrated inside a planar antenna and fed differentially by a coplanar waveguide transmission line. The antenna is placed on an extended hemispherical high-resistivity silicon substrate lens. The local oscillator signal is swept from 3 to 5 GHz and high-order harmonic mixing in both the up- and down-conversion mode is used to realize the RF bandwidth. The network analyzer has a dynamic range of >;50 dB in a 1-kHz bandwidth, and was successfully used to measure frequency-selective surfaces with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> =20, 30, and 40 GHz and a second-order bandpass response. Furthermore, the system was built with circuits and components for easy scaling to millimeter-wave frequencies, which is the primary motivation for this work.

High-Performance Solenoidal RF Transformers on High-Resistivity Silicon Substrates for 3D Integrated Circuits

Soleniod-like transformers based on a traveling-wave design and using advanced through silicon via process technology are reported for operation at frequencies from 1 to 14 GHz. The symmetrical 1:1 transformers are designed as compact slow-wave transmission-line structures with well-defined signal return paths. One-, two-, three-, and four-turn transformers have 1-dB bandwidths ranging from 6 to 9.2 GHz, and midband insertion losses from 0.24 to 0.37 dB. The measured intrinsic loss is 0.46 dB or less up to 10 GHz, and 0.97 dB up to 14 GHz. Relatively simple and scalable physically based lumped-element circuit models accurately predict the performance of these low parasitic transformers.

V‐band low phase‐noise oscillator based on a cavity resonator integrated in the silicon substrate of the MCM‐D platform

AbstractIn this article, we present a V‐band low‐phase‐noise oscillator stabilized by a silicon integrated cavity resonator (SiCR). The SiCR is realized in a multi chip module‐deposited thin‐film technology platform. The high resistivity silicon substrate is thinned to 100 μm and through silicon vias are available. The resonator is formed by a double row of through silicon vias defining a TM010 cylindrical cavity resonator. The area on top of the resonator is reused for flip‐chip mounting the active device, a MMIC chip realized in BiCMOS technology, implementing SiGe heterojunction bipolar transistors. A lower phase noise is demonstrated for the oscillator using SiCR in comparison with an idle oscillator using the same active device but a shorted CPW line as resonator. In the best case, the phase‐noise of the oscillator with SiCR is reduced to −102 dBc/Hz at 1‐MHz carrier offset, fosc = 54 GHz, from −89 dBc/Hz at 1 MHz carrier offset, fosc = 47.3 GHz, corresponding to the idle oscillator, using the CPW resonator. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1788–1792, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26946

Sub-electron readout noise in a Skipper CCD fabricated on high resistivity silicon

The readout noise for Charge-Coupled Devices (CCDs) has been the main limitation when using these detectors for measuring small amplitude signals. A scientific CCD fabricated on a high-resistivity silicon substrate utilizing a floating gate amplifier with the capability of multiple sampling of the charge signal is described in this paper. The Skipper CCD architecture and its advantages for low noise applications are discussed. A technique for obtaining sub-electron readout noise levels is presented, and its noise and signal characteristics are derived. We demonstrate that with this procedure a very low readout noise of 0.2e − RMS can be achieved. The contribution of other noise sources (output stage, vertical and horizontal charge transfer inefficiency, and dark current noise) are also considered. The optimum number of samples for achieving the total lowest possible noise level is obtained. This technique is applied to an X-rays experiment using a 55Fe source.

Transmission Performances of CPW Lines on a Laser-Crystallization Polysilicon Passivated High-Resistivity Silicon Substrate

In this paper, we report the preparation of polycrystalline silicon by excimer laser-crystallization of amorphous silicon α and its use as a surface-passivation layer (SPL) on high-resistivity silicon (HR-Si) substrates. The transmission loss (α <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TL</sub> ) of coplanar waveguide (CPW) lines on an oxide-coated HR-Si substrate with a 100-nm excimer laser-annealed (ELA) SPL is less than 1.16 dB/cm at frequencies up to 20 GHz. Therefore, an ELA-SPL is capable of providing good surface passivation for radio-frequency integrated circuit applications. The influence of geometric parameters on the transmission characteristics of the CPW lines is also studied. Extracted material parameters and equivalent lumped elements are used to interpret the loss mechanisms.

Coupled microstrip line microwave phase shifter using ferroelectric thin film varactors

This article presents a coupled microstrip line microwave phase shifter using ferroelectric thin film varactors with parallel plate electrodes integrated on high-resistivity silicon substrate. This design is proposed as a component in low-cost beam scanning phased array antennas. The phase shifter structure consists of coupled microstrip line periodically loaded with eight BaxSr1-xTiO3 (BST) varactors and two planar Marchand baluns. The planar Marchand baluns work as the transformers of odd mode excitation and a transmission stop circuit for even mode excitation as well as the impedance matching networks. A differential phase shift of 45° was obtained with a low dc bias of 20 V at frequency of 9 GHz, which corresponds to a figure of merit of ∼23°/dB. These results represent significant progress toward compact size, low loss, and ferroelectric thin film-based phase shifters at room temperature.

Design of a MEMS Broadband Microstrip Patch Antenna Based on Minkowski Fractal Boundary

A MEMS broadband microstrip patch antenna based on Minkowski fractal boundary is designed. An air layer is designed in the antenna’s high resistance silicon substrate by MEMS technology and microstrip patch antenna with second degree iteration Minkowski fractal boundary is simulated. Then different p on the influence on the broadband performance of the antenna is discussed. The simulation results show that the broadband performance can be gained from microstrip patch antenna with MEMS air layer based on second iteration Minkowski fractal boundary. 23.34% relative bandwidth of the optimized antenna is achieved and the requirement of the broadband communication is satisfied.

435mS/mm transconductance for AlGaN/GaN HEMTs on HR-Si substrate with optimised gate-source spacing

A report is presented on high transconductance Gm measured on AlGaN/GaN HEMTs with a 12.5 nm-thick AlGaN barrier layer, grown on high resistivity silicon substrate using the MOCVD growth technique. 105 nm T-gate transistors were successfully fabricated using Pt/Ti/Pt/Au Schottky contact. Maximum current density of 723 mA/mm, current gain cutoff frequency of 80 GHz and maximum power gain cutoff frequency of 153 GHz are achieved. The devices feature a record peak extrinsic transconductance of 435 mS/mm which to the authors&apos; knowledge is the highest reported value for AlGaN/GaN HEMTs grown on Si (111). Different gate-source (Lgs) and drain-source (Lds) spacing were also designed to study their influence on the electrical device characteristics. The devices were fabricated in the framework of a tight collaborative project between OMMIC and IEMN.

Broadband Branch Line Balun using Meander line on Silicon Substrate

This article presents the design of L-band branch line balun using microstrip configuration on high resistive silicon substrate (ρ>8KΩ-cm). In comparison to earlier designs better performance is achieved by meandering all the four branches and appending a quarter wavelength short circuited stub at the upper right corner of the structure. The circuit is designed using circuit simulator of Agilent's advanced design system (ADS) and further verified using Ansoft's FEM and ADS's MoM based electromagnetic solvers. Comparative study is carried out among various simulation techniques and analyzed. Fabrication methodology along with design steps are detailed in this article. Proposed design saves around 60% print area as compared to conventional topology. Further comparison with other reported topologies have also been discussed. Keywords - Branch line balun, high resistive silicon, microstrip line, short circuited stub, via hole.

A Novel Wafer-Level Double Side Packaging and Its Microwave Performance

In this paper, a wafer-level System-in-Packaging structure using through silicon via (TSV) for integration on both sides of the silicon wafer is presented. It is composed of BCB/ metal multilayers, high-resistivity silicon substrate with TSV. To reduce the transmission loss in microwave frequency, not only the high-resistivity silicon is used, but also a special TSV structure with 6 grounded shielding vias around the core via are adopted. Microstrip line (MSL) is used to transmit high-frequency signal on package plane together with the low permittivity intermediate dielectric polymer, BCB. Descriptions on the interconnection structure and the fabrication process are included. The microwave measurement result of the MSL connected by TSVs is measured up to 35GHz. The results of both the simulation and the measurement are presented.

Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

Substrate crosstalk into standard and trap-rich high-resistivity silicon (HR-Si) substrates over a wide frequency range, from ultralow frequency (ULF) to extremely high-frequency band (EHF), is investigated using finite-element numerical simulations and experiments. It is demonstrated that low-frequency substrate crosstalk is strongly impacted by the presence of free carriers at the interface between the HR-Si substrate and the interconnection passivation layers. The efficiency of a trap-rich layer, a polysilicon layer thicker than 300 nm, placed at that interface to recover the nominal high-resistivity characteristic of the Si substrate is theoretically and experimentally demonstrated. Finally, the wideband crosstalk behavior of the HR-Si substrate with and without a trap-rich layer is modeled by means of a simple equivalent lumped-element circuit. The proposed model shows excellent agreement with finite-element numerical simulations and experimental data for frequencies above 100 kHz. Due to the introduction of a trap-rich layer, HR-Si substrate behaves as a lossless dielectric substrate. In that case, a purely capacitive electrical equivalent circuit is sufficient to properly describe the substrate crosstalk characteristics.

Microwave evaluation of Pb0.4Sr0.6TiO3 thin films prepared by magnetron sputtering on silicon: Performance comparison with Ba0.3Sr0.7TiO3 thin films

Pb0.4Sr0.6TiO3 (PST) thin films were deposited on high resistivity silicon substrate by radio frequency magnetron sputtering. A pure perovskite phase was obtained at a low post annealing temperature of 650 °C. The relative dielectric constant, loss factor, tenability, and figure of merit were determined over a large frequency range of 1 GHz to 60 GHz. A large tunability about 60% and a relatively low loss of 16% at 60 GHz were obtained. PST is an alternative material for microwave agile devices integrated with silicon and this is discussed from the standpoint of monolithic integration with a low thermal budget.

Rapid Thermal Treatment for Improving Thermal Processing Stability of Ar-Implanted Surface Passivated High-Resistivity Silicon

This study improved the thermal processing stability of Si-based coplanar waveguides (CPW) through Ar ion implantation with rapid thermal annealing (RTA). Ar ion implantation damaged the surface layer of the high-resistivity silicon substrate, which decreased attenuation of the CPW line. However, the damaged layer recrystallized during a high temperature process, which caused thermal processing instability. A RTA process was performed to retard the epitaxial regrowth from the substrate, this improved thermal processing stability and decreased dc-voltage dependence of the attenuation of the CPW line. These improved properties were found to be due to the RTA process retaining more bulk traps within the damaged layer.

RF MEMS Metal-Contact Switches With mN-Contact and Restoring Forces and Low Process Sensitivity

This paper presents an electrostatic RF microelectromechanical systems (MEMS) metal contact switch based on a tethered cantilever topology. The use of tethers results in a design that has low sensitivity to stress gradients, biaxial stresses, and temperature. A switch with a footprint of 160 × 190 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and based on a 8-μm-thick gold cantilever with an Au/Ru contact is implemented on a high-resistivity silicon substrate and results in a total contact force of 0.8-1.2 mN at 80-90 V, a restoring force of 0.5 mN, a pull-in voltage of 61 V, an up-state capacitance of 24 fF, and an actuation time of 6.4 μ s. The device achieves a switch resistance of 2.4±1.4 Ω to 1.8±0.6 Ω at 90-100 V in open laboratory environments (nonpackaged). This design has the potential to replace conventional electromagnetic relays in application areas such as automated testing equipment and high-performance switching networks.

Extraction and Analysis of Substrate Parameters in On-Chip Spiral Inductor Model

Inductors on high resistivity substrate, such as quartz or high resistivity silicon(HR-Si), can get better Q factor than those on low resistivity substrate, which makes it necessary to research the substrate influence on inductors. In this paper, a lumped element model for on-chip inductor that includes skin and proximity effects, substrate electric and magnetic losses at high-frequency range is presented. The proposed model has been verified with square spiral inductors with various geometrical configurations on quartz, SOI and high-resistivity silicon substrate. It shows good agreement with the simulation and tested results. This model can be easily used in circuit simulations and optimization design.