High-quality Dielectric Layer Research Articles

Preparation of Low-Temperature Solution-Processed High-κ Gate Dielectrics Using Organic-Inorganic TiO2 Hybrid Nanoparticles.

Organic-inorganic hybrid dielectric nanomaterials are vital for OTFT applications due to their unique combination of organic dielectric and inorganic properties. Despite the challenges in preparing stable titania (TiO2) nanoparticles, we successfully synthesized colloidally stable organic-inorganic (O-I) TiO2 hybrid nanoparticles using an amphiphilic polymer as a stabilizer through a low-temperature sol-gel process. The resulting O-I TiO2 hybrid sols exhibited long-term stability and formed a high-quality dielectric layer with a high dielectric constant (κ) and minimal leakage current density. We also addressed the effect of the ethylene oxide chain within the hydrophilic segment of the amphiphilic polymer on the dielectric properties of the coating film derived from O-I TiO2 hybrid sols. Using the O-I TiO2 hybrid dielectric layer with excellent insulating properties enhanced the electrical performance of the gate dielectrics, including superior field-effect mobility and stable operation in OTFT devices. We believe that this study provides a reliable method for the preparation of O-I hybrid TiO2 dielectric materials designed to enhance the operational stability and electrical performance of OTFTs.

Effects of atmospheric UV-O3 exposure of WSe2 on the properties of the HfO2/WSe2 interface

Transition metal dichalcogenides (TMDCs), such as semiconducting WSe2, are typically interfaced with a high-quality dielectric layer in device applications. The unreactive basal plane of TMDCs makes the standard technique for deposition of dielectric oxides, atomic layer deposition (ALD), challenging on TMDC surfaces. In this work, we make use of atmospheric ultraviolet–ozone (UV-O3) exposure of WSe2 to functionalize its surface and promote uniform ALD of HfO2. We report two classifications depending on the UV-O3 exposure time. Low exposures do not result in detectable WSe2 surface oxidation, while high exposures result in a self-limiting and amorphous tungsten oxyselenide top layer. Following ALD of HfO2, low exposure samples have an abrupt HfO2/WSe2 interface with no interfacial oxide, while high exposure results in an interfacial WO3 layer between the HfO2 and the WSe2, as well as evidence of two doping states observed in the underlying WSe2. Despite differences in the interface chemistry, both low and high exposures result in uniform and smooth HfO2 films directly deposited by ALD and a reduction in gate leakage through this HfO2 layer. We report that our atmospheric UV-O3 exposure technique on WSe2 is an avenue for allowing direct ALD of thin uniform oxide films on WSe2, and the UV-O3 exposure time provides unique tunability and flexibility in interface design within devices.

β -Ga2O3 trench Schottky diodes by low-damage Ga-atomic beam etching

β -Ga2O3 trench Schottky barrier diodes fabricated through a Gallium atomic beam etching technique with excellent field strength and power device figure of merit are demonstrated. Trench formation was accomplished by a low-damage Ga flux etch that enables near-ideal forward operating characteristics that are independent of fin orientation. The reverse breakdown field strength of greater than 5.10 MV/cm is demonstrated at a breakdown voltage of 1.45 kV. This result demonstrates the potential for Ga atomic beam etching and high-quality dielectric layers for improved performance in β-Ga2O3 vertical power devices.

Gate dielectric layer mitigated device degradation of AlGaN/GaN-based devices under proton irradiation

In this study, the simulations of AlGaN/GaN-based devices, including AlGaN/GaN high electron mobility transistor (HEMT), Al2O3 metal–oxide–semiconductor high electron mobility transistor (MOSHEMT), and SiNx metal–insulator–semiconductor high electron mobility transistor (MISHEMT), were studied to investigate the degradation mechanism after proton irradiation. The vacancies produced by proton irradiation, especially Ga vacancy (VGa), are found to be responsible for the device degradation by carrier removal and mobility degradation, which directly influence the saturation drain current and maximum transconductance of AlGaN/GaN-based devices. Furthermore, AlGaN/GaN HEMTs with gate dielectrics (Al2O3, SiNx) exhibit better irradiation resistance than traditional AlGaN/GaN HEMTs, which produce fewer vacancies at the channel after proton irradiation. Al2O3 MOSHEMTs also show better performance than SiNx MISHEMTs in resisting proton damage. Therefore, a high-quality dielectric layer is a key factor to improve the reliability of AlGaN/GaN-based devices after proton irradiation.

High mobility achieved in InGaZnO TFT with vacuum-gap as insulating layer

In this Letter, an amorphous In-Ga-Zn-O (InGaZnO) thin-film transistor (TFT) structure with a vacuum-gap as a dielectric layer is proposed and investigated. Field-effect conduction at the vacuum/InGaZnO interfaces exhibits extraordinary effective mobility (μ) up to 65 ± 20 cm2 V−1 s−1, while the μ is only around 10 cm2 V−1 s−1 at the SiO2/InGaZnO interfaces with similar film processing conditions. Temperature-dependent transport is performed for deeper insight of the physical origin of the much higher μ at the vacuum/InGaZnO interface. We have found the density of states (DOS) of tail states is notably lower for the transport near the vacuum (8 × 1017 compared to 1.1 × 1019 cm−3 eV−1 at the SiO2/vacuum interface). These indicate that traditional dielectric materials like SiO2 have strong effects on the charge transport degradation in InGaZnO TFTs by introducing extra energetic disorders, and the intrinsic charge transport in InGaZnO is potentially approaching those in poly-silicon TFTs. Exploring a high-quality dielectric layer should be one effective way to further optimize the electrical performance in TFTs based on amorphous oxide semiconductors.

Mechanical strain and electric-field modulation of graphene transistors integrated on MEMS cantilevers

This work proposes a structure which allows characterization of graphene monolayers under combined electric field and mechanical strain modulation. Our approach is based on a cantilever integrated into a two-dimensional graphene-based Field effect transistor (FET). This allows us to change graphene properties either separately or together via two methods. The first way involves electric field induced by the gate. The second is induction of mechanical strain caused by external force pushing the cantilever up or down. We fabricated devices using silicon-on-insulator wafer with practically zero value of residual stress and a high-quality dielectric layer which allowed us to precisely characterize structures using both mentioned stimuli. We used the electric field/strain interplay to control resistivity and position of the charge neutrality point often described as the Dirac point of graphene. Furthermore, values of mechanical stress can be obtained during the preparation of thin films, which enables the cantilever to bend after the structure is released. Our device demonstrates a novel method of tuning the physical properties of graphene in silicon and/or complementary metal-oxide-semiconductor technology and is thus promising for tunable physical or chemical sensors.

A chemisorbed interfacial layer for seeding atomic layer deposition on graphite.

The integration of graphene, and more broadly two-dimensional materials, into devices and hybrid materials often requires the deposition of thin films on their usually inert surface. As a result, strategies for the introduction of surface reactive sites have been developed but currently pose a dilemma between robustness and preservation of the graphene properties. A method is reported here for covalently modifying graphitic surfaces, introducing functional groups that act as reactive sites for the growth of high quality dielectric layers. Aryl diazonium species containing tri-methoxy groups are covalently bonded (grafted) to highly oriented pyrolytic graphite (HOPG) and graphene, acting as seeding species for atomic layer deposition (ALD) of Al2O3, a high-κ dielectric material. A smooth and uniform dielectric film growth is confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM) and electrical measurements. Raman spectroscopy showed that the aryl groups gradually detach from the graphitic surface during the Al2O3 ALD process at 150 °C, with the surface reverting back to the original sp2-hybridized state and without damaging the dielectric layer. Thus, the grafted aryl groups can act as a sacrificial seeding layer after healing the defects of the graphitic surface with annealing treatment.

Tuning the high-κ oxide (HfO2, ZrO2)/4H-SiC interface properties with a SiO2 interlayer for power device applications

SiC based power devices are promising for the next generation energy-efficient power converters. But its device performance is always largely limited by the tradition thermal SiO2 gate dielectric. The high-κ dielectric gate oxides have been widely used in Si and III-V devices. However, high quality dielectric layer using high-κ oxide for SiC power device is still lacking sufficient theoretical investigation. In this paper, the properties of XO2/4H-SiC (X = Hf or Zr) interfaces with a SiO2 interlayer are systematically studied by density-functional supercell calculations. Reliable interface atomic structures without any gap states have been built according to the electron counting rule. Based on the models, the electronic structure of each interface is obtained by hybrid functional. The interfacial characteristics including the averaged potential and charge transfer analysis are calculated in detail. The calculated band edge line-ups are comparable with the experimental reports. In term of the band alignment, HfO2 and ZrO2 directly bonding to SiC are not suitable dielectric materials for SiC based power device, due to the relatively smaller conduction band offsets (CBO). While introducing the SiO2 interlayer can effectively tune the interface properties, especially the band alignment. With HfO2(ZrO2)/SiO2 stack as the dielectric layer for 4H-SiC, the interface has the large CBO (>1 eV) to efficaciously confine the channel carriers, indicating that the HfO2(ZrO2)/SiO2/4H-SiC stack is the promising strategy for SiC based power device applications.

Facile Synthesis of Solution-Processed Silica and Polyvinyl Phenol Hybrid Dielectric for Flexible Organic Transistors.

A high-quality dielectric layer is essential for organic thin-film transistors (OTFTs) operated at a low-power consumption level. In this study, a facile improved technique for the synthesis of solution-processed silica is proposed. By optimizing the synthesis and processing technique fewer pores were found on the surface of the film, particularly no large holes were observable after improving the annealing process, and the improved solution–gelation (sol–gel) SiOx dielectric achieved a higher breakdown strength (1.6 MV/cm) and lower leakage current density (10−8 A/cm2 at 1.5 MV/cm). Consequently, a pentacene based OTFT with a high field effect mobility (~1.8 cm2/Vs), a low threshold voltage (−1.7 V), a steeper subthreshold slope (~0.4 V/dec) and a relatively high on/off ratio (~105) was fabricated by applying a hybrid gate insulator which consisted of improved sol–gel SiOx and polyvinyl phenol (PVP). This could be ascribed to both the high k of SiOx and the smoother, hydrophobic dielectric surface with low trap density, which was proved by atomic force microscopy (AFM) and a water contact angle test, respectively. Additionally, we systematically studied and evaluated the stability of devices in the compressed state. The devices based on dielectric fabricated by conventional sol–gel processes were more susceptible to the curvature. While the improved device presented an excellent mechanic strength, it could still function at the higher bending compression without a significant degradation in performance. Thus, this solution-process technology provides an effective approach to fabricate high-quality dielectric and offers great potential for low-cost, fast and portable organic electronic applications.

Electrical characterization of thin nanoscale SiOx layers grown on plasma hydrogenated silicon

We analyzed the electrical characteristics of MOS structures with a SiOx layer grown on Si treated in plasma without heating. The hysteresis effect observed indicates the presence of traps spatially distributed into the oxide near the interface. The shift and the shape of the curves reveal a small oxide charge and low leakage currents, i.e. a high-quality dielectric layer. The generalized C-V curve was generated by applying the two-frequency methods on the C-V and G-V characteristics at frequencies in the range from 1 kHz to 300 kHz and by accounting for the series resistance and the leakage through the oxide layer. The energy spectra of the interface traps were calculated by comparing the experimental and the ideal theoretical C-V curves. The spectra showed the presence of interface traps with localized energy levels in the Si bandgap. These conclusions correlate well with the results on this oxide’s mechanical stress level, composition and Si-O ring structure, as well as on the interfacial region composition, obtained by our previous detailed multi-angle spectral ellipsometric studies. The ellipsometric data and the capacitance in strong accumulation of the C-V curves were used to calculate the thickness and the dielectric constants of the oxide layers.

Growth Behavior Evolution of Al2O3 Deposited on HOPG by Atomic Layer Deposition

Abstract Al2O3 dielectrics were fabricated on highly ordered pyrolytic graphite (HOPG) by atomic layer deposition (ALD) and the effects of growth temperatures and number of ALD cycles on growth behaviors were studied. It is found that Al2O3 preferentially grows along the step edges which promote the formation of Al2O3 nanowires at the initial stage. Al2O3 nanowires can exist after 100 ALD cycles at 50, 150, and 200 °C, but discontinuous Al2O3 thin films rather than nanowires are evidenced at 100 °C. Moreover, the Al2O3 layers evolve into continuous thin films with increasing number of ALD cycles. It suggests the growth behavior undergoes a transition from three-dimensional mode to quasi two-dimensional mode with increasing number of ALD cycles. The rates of transition and lateral growth are dependent on growth temperatures. Raman spectra indicate that HOPG maintains undamaged and greatly reserves its original properties after the deposition of Al2O3. The results are of great significance to the fabrication of high-quality dielectric layers on graphene as well as the related devices.

Features of the surface morphology of CaF2/Si(100) films obtained by solid-phase epitaxy

The dielectric parameters of calcium fluoride films grown on the Si(100) surface by solid-phase epitaxy (group 2) and without it (group 1) are analyzed. It is established experimentally that the deposition mode of CaF2 films immediately after growth of the Si buffer layer at a substrate temperature of 530°C is not suitable for producing high-quality dielectric layers. The use of solid-phase epitaxy at the initial stage of the nucleation of CaF2 layers enables the production of single crystal uniformly thick films with high dielectric properties.

Efficient organic photomemory with photography-ready programming speed.

We propose a device architecture for a transistor-type organic photomemory that can be programmed fast enough for use in electrical photography. Following the strategies used in a flash memory where an isolated charge storage node or floating gate is employed, the proposed organic photomemory adopts an isolated photo-absorption zone that is embedded between upper and lower insulator layers without directly interfacing with a semiconductor channel layer. This isolated photo-absorption zone then allows the device to operate in electrically ‘on’ state, in which the high electric-field region can have a maximal spatial overlap with the illuminated area for efficient and facile light-programming. With the proposed approach, a significant threshold voltage shift is attained even with the exposure time as short as 5 ms. High quality dielectric layers prepared by initiated chemical vapor deposition ensure erasing to occur only with electrical signal in a controlled manner. Retention time up to 700 s is demonstrated.

Electrical Characterization of Epitaxial Graphene Field-Effect Transistors with High-k Al<sub>2</sub>O<sub>3</sub> Gate Dielectric Fabricated on SiC Substrates

Top-gated field-effect transistors have been created from bilayer epitaxial graphene samples that were grown on SiC substrates by a vacuum sublimation approach. A high-quality dielectric layer of Al2O3 was grown by atomic layer deposition to function as the gate oxide, with an e-beam evaporated seed layer utilized to promote uniform growth of Al2O3 over the graphene. Electrical characterization has been performed on these devices, and temperature-dependent measurements yielded a rise in the maximum transconductance and a significant shifting of the Dirac point as the operating temperature of the transistors was increased.

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors.

A silicon oxide gate dielectric was synthesized by a facile sol-gel reaction and applied to solution-processed indium oxide based thin-film transistors (TFTs). The SiOx sol-gel was spin-coated on highly doped silicon substrates and converted to a dense dielectric film with a smooth surface at a maximum processing temperature of T = 350 °C. The synthesis was systematically improved, so that the solution-processed silicon oxide finally achieved comparable break downfield strength (7 MV/cm) and leakage current densities (<10 nA/cm(2) at 1 MV/cm) to thermally grown silicon dioxide (SiO2). The good quality of the dielectric layer was successfully proven in bottom-gate, bottom-contact metal oxide TFTs and compared to reference TFTs with thermally grown SiO2. Both transistor types have field-effect mobility values as high as 28 cm(2)/(Vs) with an on/off current ratio of 10(8), subthreshold swings of 0.30 and 0.37 V/dec, respectively, and a threshold voltage close to zero. The good device performance could be attributed to the smooth dielectric/semiconductor interface and low interface trap density. Thus, the sol-gel-derived SiO2 is a promising candidate for a high-quality dielectric layer on many substrates and high-performance large-area applications.

Synthesis of large single-crystal hexagonal boron nitride grains on Cu-Ni alloy.

Hexagonal boron nitride (h-BN) has attracted significant attention because of its superior properties as well as its potential as an ideal dielectric layer for graphene-based devices. The h-BN films obtained via chemical vapour deposition in earlier reports are always polycrystalline with small grains because of high nucleation density on substrates. Here we report the successful synthesis of large single-crystal h-BN grains on rational designed Cu-Ni alloy foils. It is found that the nucleation density can be greatly reduced to 60 per mm(2) by optimizing Ni ratio in substrates. The strategy enables the growth of single-crystal h-BN grains up to 7,500 μm(2), approximately two orders larger than that in previous reports. This work not only provides valuable information for understanding h-BN nucleation and growth mechanisms, but also gives an effective alternative to exfoliated h-BN as a high-quality dielectric layer for large-scale nanoelectronic applications.

Polyimide Dielectric Layer on Filaments for Organic Field Effect Transistors: Choice of Solvent, Solution Composition and Dip-Coating Speed

Abstract In today’s research, smart textiles is an established topic in both electronics and the textile fields. The concept of producing microelectronics directly on a textile substrate is not a mere idea anymore and several research institutes are working on its realisation. Microelectronics like organic field effect transistor (OFET) can be manufactured with a layered architecture. The production techniques used for this purpose can also be applied on textile substrates. Besides gate, active and contact layers, the isolating or dielectric layer is of high importance in the OFET architecture. Therefore, generating a high quality dielectric layer that is of low roughness and insulating at the same time is one of the fundamental requirements in building microelectronics on textile surfaces. To evaluate its potential, we have studied polyimide as a dielectric layer, dip-coated onto copper-coated polyester filaments. Accordingly, the copper-coated polyester filament was dip-coated from a polyimide solution with two different solvents, 1-methyl-2-pyrrolidone (NMP) and dimethylformaldehyde. A variety of dip-coating speeds, solution concentrations and solvent-solute combinations have been tested. Their effect on the quality of the layer was analysed through microscopy, leak current measurements and atomic force microscopy (AFM). Polyimide dip-coating with polyimide resin dissolved in NMP at a concentration of 15w% in combination with a dip-coating speed of 50 mm/min led to the best results in electrical insulation and roughness. By optimising the dielectric layer’s properties, the way is paved for applying the subsequent semi-conductive layer. In further research, we will be working with the organic semiconductor material TIPS-Pentacene

Natural resin shellac as a substrate and a dielectric layer for organic field-effect transistors

Biocompatible and sustainable electronic-grade materials are integral for the development of electronics for biointegration and ‘use-and-throw’ applications. Herein we report the use of the natural resin shellac in organic field-effect transistors. Shellac was employed to cast robust and smooth substrates suitable for durable transistor devices. In addition shellac displays excellent insulating properties enabling its use as a high-quality dielectric layer for organic field-effect transistor (OFET) devices. We demonstrate that two common organic semiconductors, pentacene and C60, show hysteresis-free operation in OFETs that employ shellac both as the substrate and as dielectric material. Shellac is a fully biocompatible (even edible) material that offers many advantages for OFET fabrication, including high dielectric breakdown fields, simple solution processing from ethanol solutions, and low temperature crosslinking at 50–70 °C. This work shows that shellac as a biomaterial can enable OFET applications where biocompatibility is necessary.

P-Type Tunneling Field-Effect Transistors on (100)- and (110)-Oriented Si Substrates

p-Type tunneling field-effect transistors (TFETs) on (100)- and (110)-oriented Si substrates were fabricated, and their electrical characteristics were studied. High-k dielectric and metal gate were integrated as a gate stack, and the gate-last process was performed to obtain a high-quality dielectric layer and prevent crystallization. The orientation effect of p-type TFETs on (100) and (110) Si wafers is a high ION in the case of the (110) orientation as compared with that of the (100) p-type TFET, which is a high band-to-band tunneling current. The junction profile and effective mass were discussed to determine possible reasons for the orientation effect of p-type TFETs on (100) and (110) Si wafers.

Ozone Based Atomic Layer Deposition of Hafnium Oxide and Impact of Nitrogen Oxide Species

It has recently been reported that nitrogen oxide species (e.g., N2O5, NO2, NO3, and/or N2O) can have an impact on ozone based atomic layer deposition (ALD) of metal oxides when ozone is generated by dielectric barrier discharge (DBD) in O2/N2 mixtures. In this work, we further investigate the effect of the O2/N2 ratio in the DBD for HfO2 ALD using HfCl4 as metal precursor. Using O3 in the absence of nitrogen oxides, uniform HfO2 layers are obtained between 200 and 250°C in a hot wall cross flow reactor. The self-limiting nature of the O3 and HfCl4 reaction is demonstrated at 225°C and the growth-per-cycle is 0.12 nm. At higher temperature, O3 decomposes at the HfO2 coated reactor walls, resulting in a decreasing HfO2 thickness over Si substrates in the direction of the gas flow. Using O3 in combination with nitrogen oxides by DBD in N2/O2 mixtures, we obtained uniform HfO2 layers in the 200–300°C temperature range. At 300°C, the GPC is 0.14 nm and the HfO2 films show a low impurity content. Both processes produce high quality dielectric layers in Pt gated capacitors.