High Power Supply Rejection Research Articles

High-PSRR low-power single supply OTA

A CMOS single supply operational transconductance amplifier (OTA) is reported. It has high power supply rejection capabilities over the entire gain bandwidth. The OTA is fabricated using the AMI 0.5 m CMOS process. Measurements show power supply rejection ratio (PSRR) of 120 dB to 10 kHz. At 10 MHz, PSRR is 40 dB. The high performance PSRR is achieved using a high impedance current source and two noise reduction techniques. The OTA offers very low current consumption of 25 A from a 3.3 V supply. It is suitable for applications such as low drop out voltage regulators.

25 mA LDO with −63 dB PSRR at 30 MHz for WiMAX

A low-dropout regulator (LDO) with high power-supply rejection ratio (PSRR) is presented. The high PSRR at high frequency is enabled by a signal-nulling technique achieved by a wide-bandwidth feedforward path. Experimental results verify the outstanding performance.

A 2.8 ppm/°C high PSRR BiCMOS bandgap voltage reference

A high-order curvature-compensated and high power-supply rejection ratio (PSRR) BiCMOS bandgap reference is presented. The circuit utilizes positive temperature characteristics of the saturation current ISS and forward current gain β of the bipolar transistors to realize a low temperature coefficient (TC) as well as filter capacitors and level-shift structures to improve the PSRR. Implemented in 0.6 μm BCD process, the proposed voltage reference consumes a supply current of 28 μA at 3.6 V. A temperature coefficient of 2.8 ppm/°C, PSRR of more than 80 dB at low frequencies and a line regulation of 50 ppm/V from 3.6 to 5.5 V are easily achieved, which make it widely applicable in portable equipment.

Noise Minimization for Low Power Bandgap Reference and Low Dropout Regulator Cores

This paper describes the techniques to design low power series low dropout regulators (LDO) with low output noise and high power supply rejection (PSR). The noise analysis of the bandgap reference is critical to the linear regulator's output noise, since it represents the main source of noise. The necessary trade-offs that a designer faces are discussed according to the demands of modern IP cores. A precise theoretical noise analysis of a typical bandgap and LDO topology is presented, allowing the analogue designer to identify which are the trade-offs between power and noise, and decide the architecture and design criteria based on these constraints. A LDO and a bandgap with low noise, low power and high PSR are designed in a 0.35 μm CMOS technology and integrated in a Power Management Unit (PMU). No decoupling capacitor is considered in the reference's output.

A 10-bit 205-MS/s 1.0-$\hbox{mm}^{2}$ 90-nm CMOS Pipeline ADC for Flat Panel Display Applications

This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm2 in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-VPP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I–V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18μm standard CMOS logic process technology, exhibits a stable current of about 1.701μA with much low temperature coefficient of 2.5×10−4μA/°C in the temperature range of −40 to 150°C at 1.5V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126dB at dc frequency and remains −92dB at the frequency higher 1MHz. The proposed circuit operates stably at the supply voltage higher 1.2V and has good process compatibility.

A Gigabit Link CMOS Analog Interface for High Performance Signaling

In this brief, design of a gigabit link CMOS analog interface composed of a transmitter, a receiver, and clocking circuits is addressed with focus on high-performance signaling in terms of interference and jitter. The low-cost, low-power interface is targeted at parallel link applications. The transmitter adopts one-tap preemphasis to mitigate the intersymbol interference (ISI) problem. The receiver samples two adjacent bits and stores the difference of them to a capacitor, so it is more immune to timing uncertainties caused by nonideal sampling clocks and it is dependent only on the direction or difference of two consecutive bits, not on the absolute values of them. With these circuits, robust clocking circuits to multiplex and demultiplex the data on the transmit and receive side, respectively, are designed. Pseudo-differential-type delay elements are used in the oscillator and delay line to enable high power supply rejection ratio and low jitter. The delay locked loop (DLL) is designed to prevent harmonic locking. The transceiver performance is tested at 1 Gbps and 2 Gbps for double and quadruple interleaving, respectively. The maximum operating speed is about 1.7 Gbps for double interleaving and about 3 Gbps for the quadruple-interleaving receiver under a 3.3 V, 0.35 ?m CMOS process.

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm/sup 2/, a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm//spl deg/C and a standard deviation of 20 mV without trimming.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges

This paper presents a CMOS buffer amplifier which operates on a single 5-V power supply. The uniquely symmetrical design adds the following advantages: rail-to-rail linear, symmetrical operation at both the input and output; the output stage allows the use of gate channel capacitors of standard MOSFET's as the compensation capacitor saving die area from 80%/spl sim/93% in a standard single polysilicon digital process; large gain-bandwidth product; high power supply rejection ratio; good common-mode rejection ratio; and easy compact layout suitable for design automation (layout as a parametric cell, allows easy adaption to changing processes). The buffer is capable of driving 300 /spl Omega//spl par/100 pF with a loaded gain-bandwidth product of more than 4 MHz and a fully loaded slew rate of greater than 4 V//spl mu/S. >

PCM telephony: reduced architecture for a D/A converter and filter combination

Large dynamic range and high power-supply rejection ratio (PSRR) are achieved in a pulse-code-modulation (PCM) decoder by using differential circuit techniques and by reducing the number of operational amplifiers on the interpolation filter to four (including the output buffer). This reduction is achieved by: (1) exploiting the sin x/x distortion and using a simple integrating configuration in the digital-to-analog converter; and (2) properly manipulating the signal flowgraph of the filter.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.