Abstract
This paper describes the techniques to design low power series low dropout regulators (LDO) with low output noise and high power supply rejection (PSR). The noise analysis of the bandgap reference is critical to the linear regulator's output noise, since it represents the main source of noise. The necessary trade-offs that a designer faces are discussed according to the demands of modern IP cores. A precise theoretical noise analysis of a typical bandgap and LDO topology is presented, allowing the analogue designer to identify which are the trade-offs between power and noise, and decide the architecture and design criteria based on these constraints. A LDO and a bandgap with low noise, low power and high PSR are designed in a 0.35 μm CMOS technology and integrated in a Power Management Unit (PMU). No decoupling capacitor is considered in the reference's output.
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