A low noise, fast set-up low-dropout regulator in 65nm technology

Abstract

Low noise, fast set-up low-dropout (LDO) regulators are critical for noise-sensitive analog blocks, such as ADCs, PLLs, and RF SoC, etc. This paper presents a two-stage LDO regulator with low output noise, fast set-up, and high power supply rejection ratio (PSRR), based on internal noise filter with a novel fast set-up module, which solves dc shift problems. The proposed LDO is fabricated in a standard 65nm CMOS process. Measurement showed that output noise rms voltage is about 50nV/rtHz ranging from 10Hz to 100 KHz, set-up time is less than 20us, and PSRR is 65B at 1 KHz and 54dB at 1MHz.