High-permittivity Gate Dielectrics Research Articles

Single event burnout hardening of trench shielded power UMOSFET using High-κ dielectrics

This study proposes the High-κ dielectric Trench Shielded power UMOSFET (HK TS-UMOSFET) to be assessed using the two-dimensional numerical simulations. The simulations are employed to evaluate HK TS-UMOSFETs susceptibility to single-event burnout (SEB) mechanism. Based on the findings, the influence of alternative high permittivity gate dielectrics to silicon dioxide (SiO2) in TS-UMOSFET was discussed. Furthermore, in order to improve the performance of the device, its electrical behaviour was simulated with several high-κ dielectrics including Al2O3, Si3N4 and Aluminium Nitride (AlN). When heavy ions strike the sensitive areas of the device, the electric field distribution and SEB threshold values were extracted. Based on the values yielded, (AlN) was identified as a promising high-κ material to achieve SEB-hardened TS-UMOSFET compared to the other high-κ dielectrics. In conclusion, with (AlN), the HK TS-UMOSFET offers a high SEB tolerance and improved electrical characteristics.

Comprehensive and systematic design of metal/high-k gate stack for high-performance and highly reliable SiC power MOSFET

Aluminum-based high-permittivity (high-k) gate dielectrics and suitable metal electrodes were systematically designed for advanced SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs). Although electron injection into alumina (Al2O3) was significantly suppressed by nitrogen incorporation (aluminum oxynitride: AlON), gate leakage current under negative gate bias and hole trapping into the dielectrics were observed. Adding hafnium into the AlON (HfAlON) was investigated to overcome these drawbacks, and an atomic layer deposition-based method for HfAlON was developed in terms of permittivity, energy bandgap, and hole conduction under negative stressing conditions. Consequently, the reliability of metal/high-k gate stacks under both positive and negative bias temperature stresses was improved by using an optimized HfAlON gate dielectric in combination with a high work-function TiN gate electrode. Thanks to the higher permittivity of HfAlON, peak transconductance was successfully enhanced up to 3.4 times with an acceptable reliability margin in the state-of-the-art trench SiC MOSFETs by implementing a TiN/HfAlON gate stack.

Stable tetragonal phase and magnetic properties of Fe-doped HfO2 nanoparticles

In this paper, the effect in structural and magnetic properties of iron doping with concentration of 20% in hafnium dioxide (HfO2) nanoparticles is investigated. HfO2 is a wide band gap oxide with great potential to be used as high-permittivity gate dielectrics, which can be improved by doping. Nanoparticle samples were prepared by sol-gel chemical method and had their structure, morphology, and magnetic properties, respectively, investigated by X-ray diffraction (XRD), transmission electron microscopy (TEM) and scanning electron microscopy (SEM) with electron back scattering diffraction (EBSD), and magnetization measurements. TEM and SEM results show size distribution of particles in the range from 30 nm to 40 nm with small dispersion. Magnetization measurements show the blocking temperature at around 90 K with a strong paramagnetic contribution. XRD results show a major tetragonal phase (94%).

Effect of Novel Nanocomposite Materials for Enhancing Performance of Thin Film Transistor TFT Model

<span>The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La<sub>2</sub>O<sub>3</sub>K<sub>ox</sub>=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO<sub>2</sub>K<sub>sp</sub>=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.</span>

Performance Enhancement of CNTFETs with High-Κ Dielectric

The potential impact of high permittivity gate dielectrics on the performance of a ballistic nanoscale CNTFET is studied over a wide range of dielectric permittivities with low temperatures ranging from room temperature down to 100 K. Using the non-equilibrium Greens function (NEGF) formalism. Device characteristics such as ION/IOFF current ratio, threshold voltage, the drain induced barrier lowering (DIBL). The effects of temperature varying are also examined.

Fabrication of advanced La-incorporated Hf-silicate gate dielectrics using physical-vapor-deposition-based in situ method and its effective work function modulation of metal/high-k stacks

Lanthanum (La) incorporation into Hf-silicate high-permittivity (high-k) gate dielectrics was conducted using a physical-vapor-deposition (PVD)-based in situ method. PVD-grown metal Hf, La, and Hf–La alloys on base SiO2 oxides received in situ annealing to form high-quality HfLaSiO dielectrics, and subsequent deposition of metal gate electrodes was carried out to fabricate advanced metal/high-k gate stacks without breaking vacuum. The in situ method was found to precisely control La content and its depth profile and to tune the effective work function of metal/high-k stacks. Remarkable leakage current reduction of almost seven orders of magnitude compared with conventional poly-Si/SiO2 stacks and excellent interface properties comparable to an ideal SiO2/Si interface were also achieved at an equivalent oxide thickness of around 1.0 nm. Our x-ray photoelectron spectroscopy analysis revealed that, as previously suggested, effective work function modulation due to La incorporation is attributed to the interface dipole (or localized sheet charge) at the bottom high-k/SiO2 interface, which is crucially dependent on the La content at the interface. Moreover, it was found that high-temperature annealing causing interface oxide growth leads to redistribution of La atoms and forms the uppermost La-silicate layer at the metal/high-k interface by releasing the dipole moment at the bottom high-k/SiO2 interface. Based on these physical and electrical characterizations, the advantages and process guidelines for La-incorporated dielectrics were discussed in detail.

Simulation study of circuit performances of independent double-gate (IDG) MOSFETs with high-permittivity gate dielectrics

This study analyzes by 2-D numerical simulation the electrical performances of independent double-gate (IDG) MOSFET with high-permittivity (high-kappa) dielectric gate stacks. We particularly address the operation of elementary devices as well as of the associated CMOS inverters, which are investigated in terms of static power dissipation and delay. We show that the introduction of a pure high-kappa gate dielectric layer degrades the device immunity to short-channel effects and the power consumption of the CMOS inverter, but simultaneously improves the inverter speed, with respect to performances of a reference transistor with a SiO2 gate oxide with the same equivalent oxide thickness. However, in real devices, the existence of a native oxide between the high-kappa gate dielectric and the underlying semiconductor reduces parasitic electrostatic effects and sensibly improves inverter speed and power consumption. A detailed comparison between the operation of high-kappa gate stack-based double-gate devices with independent and connected gates is also presented. (C) 2009 Elsevier B.V. All rights reserved.

Scaling the MOSFET gate dielectric: From high- k to higher- k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high- k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO 2 can be scaled to capacitance equivalent thickness in inversion ( T inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high- k/channel interfacial layer. This is based on the higher dielectric constant of Si 3N 4 and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher- k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO 2 as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO 2 at the poly-Si contact. We further address the performance of Si 3N 4 and HfO 2 as oxygen barrier layers.

Study of gate dielectric permittivity variation with different equivalent oxide thickness on channel engineered deep sub-micrometer n-MOSFET device for mixed signal applications

The impact of high permittivity gate dielectrics with different equivalent oxide thickness (EOT) for conventional, low and high tilt angle halo implants on the performance of 100 nm n-MOSFETs device is studied using device simulator Synopsys ISE-TCAD. In this paper, we systematically increase the value of gate dielectric (3.9–50) and investigate its effects on conventional, low angle of tilt (10 o) and high angle of tilt (50 o) halo implants for different device parameters of 100 nm n-MOSFETs using two different EOT viz. 1.5 nm and 2.0 nm. The impact of gate dielectric permittivity along with the different angles of halo implants on short channel performance contributing to the DIBL, the subthreshold swing, I ON/ I OFF ratio, and the threshold voltage V T are studied for two different EOT thicknesses. The device has been investigated for digital performance parameters like the variation of substrate–body voltage on DIBL, I OFF, I ON and the threshold voltage V T for sub 100 nm technology generation. It has also been investigated for analog performance like trans-conductance generation factor (gm/ I D) and overall gain (gm R 0).

Fringe-induced barrier lowering (FIBL) included sub-threshold swing model for double-gate MOSFETs

A physical, compact, short-channel sub-threshold swing model for undoped-gate MOSFETs has been developed to include the fringe-induced barrier lowering effect associated with high-permittivity (high-κ) gate dielectrics. Using this new device model, we found that the degradation becomes worse when the channel length becomes shorter and both the off-state current (Ioff) and sub-threshold slope(s) rollup when κ is increased. It is indicated that a way to keep a reasonable channel length/vertical physical thickness ratio could be to suppress the FIBL effect in nanoscale DG MOSFET. The result showed that the analytical model was in agreement with the published numerical simulation over a wide range of device parameters.

On the positive channel threshold voltage of metal gate electrodes on high-permittivity gate dielectrics

Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.

Atomic Layer Deposition for CMOS Scaling: High-k Gate Dielectrics on Si, Ge, and III-V Semiconductors

We review the impact of oxide-semiconductor interface chemistry and precursor choice on the quality of novel field-effect transistor gate dielectrics grown by atomic layer deposition (ALD). Focus is on hafnium- and aluminum-based high-permittivity ('high-k') gate dielectrics on silicon and on high carrier mobility (germanium, gallium arsenide) channels. We shed light on the ways processing parameters (choice of materials; surface preparation; high-k dielectric deposition process) determine stack structure (continuity of the high-k layer; interfacial oxide thickness; detrimental channel-dielectric interactions) and hence electrical quality. Trends are rationalized based on thermodynamic properties of the semiconductors, dielectrics, and metal-organic precursors involved. This may serve as a basic guideline for ALD precursor selection.

Hydrogen Barrier Layer Against Silicon Oxidation during Atomic Layer Deposition of Al2O3 and HfO2

Growth at moderate temperatures, below , is shown to prevent interfacial silicon oxidation during atomic layer deposition of high-permittivity (high-κ) gate dielectrics on hydrogen-terminated Si(100). Trimethylaluminum, employed for aluminum oxide growth, leaves the hydrogen layer completely intact. Tetrakis(ethylmethylamido)hafnium partially scavenges the hydrogen layer during hafnium oxide nucleation, resulting in an interface composed of H-terminated silicon atoms and Si–O–Hf bridges. In both cases, high-κ dielectrics are grown without formation of interfacial . Once grown at low temperatures, subnanometer layers effectively prevent interfacial formation during subsequent growth at higher temperatures required for optimum high-κ quality. This two-step deposition scheme may thereby be useful for gate-stack scaling.

Electrical characterization of high- k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO 2/Si structure

High permittivity (high- k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO 2/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO x and SiO 2. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high- k dielectric films. The interfacial structure of the high- k dielectric film/Si was transformed from HfO x /SiO 2/Si to HfSi x O y /Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO 2. These high- k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high- k dielectric film was approximately four orders of magnitude lower than that of SiO 2.

Future semiconductor material requirements and innovations as projected in the ITRS 2005 roadmap

The international technology roadmap for semiconductors (ITRS) is a joint global effort of the semiconductor industry, the manufacturing equipment and material industry and the research community and consortia to define the future requirements and development of the semiconductor technology for the next 15 years. The ITRS started in 1992 as a US-national roadmap and became an international effort in 1998 with all major five industrial global regions (US, Japan, Taiwan, Korea and Europe) participating in its definition. The outlook in semiconductor manufacturing expects the continuous application of silicon technology for the next 15 years where complementary metal oxide semiconductor (CMOS) based devices will carry the development of the industry at least for one more decade. New device architectures and concepts based on silicon wafer material are being developed to support the development of the IC industry for another one or two decade. The major section of the ITRS contains technical information about frontend processing and interconnects, device structures and memory concepts, lithography and metrology as well as factory integration and environmental issues. This paper will review the material requirements and the expected material innovations for the industry as outlined in the ITRS Version 2005. Materials to be discussed are, for example, high permittivity gate dielectrics, insulating layers with low dielectric constants for interconnects, and capacitor dielectrics for dynamic memories. In addition, the paper will address, for example, new transistor gate materials, new solutions for interconnect systems beyond copper as well as new starting materials for wafer sizes beyond 300 mm. This publication was presented as an invited paper in the Symposium V of the 2006 spring meeting of the European Materials Research Society (E-MRS) in Nice, May 29th.

The use of narrow nuclear resonances in the study of alternative metal-oxide–semiconductor structures

Narrow resonances (FWHM∼100eV) in the cross-section curves of nuclear reactions induced by protons in several light nuclei have been widely exploited in order to determine light nuclei depth profiles with nanometric near-surface depth resolution. In this paper the principles of narrow nuclear resonant reaction profiling are discussed as well as the mathematical modeling used to extract depth profiles from excitation curves. Application of the technique to the study of metal-oxide–semiconductor structures alternative to the well-established poly-Si/SiO2/c-Si is here highlighted. 15N, 18O, 27Al and 29Si depth profiles in high permittivity gate dielectrics (alternatives to SiO2), fully silicided metal gates (alternatives to poly-Si) or SiO2 grown on SiC (alternative to Si) are determined in order to understand the composition and atomic transport of the species in the materials and serve as examples of the power and flexibility of the technique.

Oxide muonics: II. Modelling the electrical activity of hydrogen in wide-gap andhigh-permittivity dielectrics

Following the prediction and confirmation that interstitial hydrogen forms shallow donorsin zinc oxide, inducing electronic conductivity, the question arises as to whether itcould do so in other oxides, not least in those under consideration as thin-filminsulators or high-permittivity gate dielectrics. We have screened a wide selectionof binary oxides for this behaviour, therefore, using muonium as an accessibleexperimental model for hydrogen. New examples of the shallow-donor states that arerequired for n-type doping are inferred from hyperfine broadening or splittingof the muon spin rotation spectra. Electron effective masses are estimated (forseveral materials where they are not previously reported) although polaronic ratherthan hydrogenic models appear in some cases to be appropriate. Deep states arecharacterized by hyperfine decoupling methods, with new examples found of theneutral interstitial atom even in materials where hydrogen is predicted to havenegative-U character, as well as a highly anisotropic deep-donor state assigned to a muonium–vacancycomplex. Comprehensive data on the thermal stability of the various neutral states aregiven, with effective ionization temperatures ranging from 10 K for the shallow to over1000 K for the deep states, and corresponding activation energies between tens of meV andseveral eV. A striking feature of the systematics, rationalized in a new model, isthe preponderance of shallow states in materials with band-gaps less below 5 eV,atomic states above 7 eV, and their coexistence in the intervening threshold range,5–7 eV.

Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics

An analytical model of the threshold voltage for long channel double-gate metal-oxide-semiconductor field effect transistor is developed, applicable to both symmetric and asymmetric structures with thin films (<10 nm) and high-permittivity gate dielectrics (with permittivities > 10). The model takes into account short-channel effects, carrier quantization and fringing-field induced barrier lowering induced by the high-permittivity gate layer. The model assumes a parabolic dependence of the potential with position in the silicon film at threshold, enabling the development of an analytical expression for the surface potential. Compared to previous models only derived for undoped films, the present approach considers both mobile charge and depleted charge terms in Poisson’s equation. The model is fully validated by numerical simulation and is used to predict the impact of the fringing-induced barrier lowering on the threshold voltage of double-gate devices as a function of the gate stack composition and the device gate length.

Molecular-dynamics study of interfacial diffusion between high-permittivity gate dielectrics and germanium substrates

The stability of interfaces with germanium, which has recently been discussed as a replacement for silicon in ultra-large-scale integrated circuits (ULSIs), was studied. Interfacial oxygen diffusion from high-permittivity gate dielectrics (ZrO2 and HfO2) into germanium substrates must be suppressed to prevent the formation of interfacial layers between the gate dielectrics and the germanium substrates. Oxygen diffusion was simulated through a molecular-dynamics technique that takes into account many-body interactions and charge transfer between different elements. The simulation results show that the addition of yttrium is effective in suppressing interfacial oxygen diffusion at the ZrO2/germanium interfaces. On the other hand, the addition of yttrium is not effective in suppressing interfacial oxygen diffusion at the HfO2/germanium interfaces. The results also show that the diffusion at the ZrO2/Ge(111) and HfO2/Ge(111) interfaces is much more suppressed than the diffusion at the ZrO2/Ge(001) and HfO2/Ge(001) interfaces.

Hf O 2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition

High-performance metal-oxide-semiconductor field effect transistors (MOSFETs) on III–V semiconductors have long proven elusive. High-permittivity (high-κ) gate dielectrics may enable their fabrication. We have studied hafnium oxide and aluminum oxide grown on gallium arsenide by atomic layer deposition. As-deposited films are continuous and predominantly amorphous. A native oxide remains intact underneath HfO2 during growth, while thinning occurs during Al2O3 deposition. Hydrofluoric acid etching prior to growth minimizes the final interlayer thickness. Thermal treatments at ∼600°C decompose arsenic oxides and remove interfacial oxygen. These observations explain the improved electrical quality and increased gate stack capacitance after thermal treatments.