High-performance VLSI Research Articles

An Area-Efficient Unified VLSI Architecture for Type IV DCT/DST Having an Efficient Hardware Security with Low Overheads

This paper introduces an efficient solution for designing a unified VLSI implementation for type IV DCT/DST while solving one challenging problem in obtaining high performance VLSI chips for common goods, which is solving the security of the hardware while obtaining a VLSI implementation with high performance. The new solution uses a new systolic array algorithm for type IV DST that can allow us to obtain an efficient unified VLSI architecture with one previously designed for type IV DCT. The proposed method uses special arithmetic structures that have been called quasi-cycle convolutions that can be efficiently mapped on linear systolic arrays. Moreover, the obtained unified VLSI architecture, besides being an efficient implementation with a low hardware complexity and high-speed performance, allows for an efficient inclusion of the obfuscation technique with very low overheads.

High Performance VLSI Architecture for DC and Planar Modes of Intra Prediction in HEVC

Abstract: High Efficiency Video Coding (HEVC) achieves improved compression efficiency, but it introduces higher computational complexity due to intricate partitioning and increased angular modes in intra prediction. In this study, we propose a hardware architecture for handling the direct current (DC) and planar modes of intra prediction in the HEVC standard. To evaluate our proposed architecture, we performed synthesis using both TSMC 180nm and TSMC 90nm technologies. We later conducted physical implementation using Physical Cell 90nm technology. The results show significant improvements when moving from TSMC 180nm to TSMC 90nm technology, with the chip area reducing by approximately three times and power consumption decreasing by over six times. After completing the physical layout phase, we obtained a chip area of 112.19 mm2 and a power consumption of 3.88 mW. Comparing the synthesis results with the physical design phase, we observed a slight increase in chip area by around 1.5 times, while the power consumption decreased by approximately 0.4 times. The proposed architecture achieves a throughput of 27 pixels per clock cycle and supports a block size of 16x16, with the potential for further extension

A Low Power 10T SRAM Cell with Extended Static Noise Margins is Used to Implement an 8 by 8 SRAM Array in 16nm CMOS

Abstract: Thus, it must have an ultra-low power design. Low power techniques must be used to obtain SRAM cells. First, all current high performance VLSI circuits must be designed with the 10T SRAM cell, which must also be checked for write and data storage capabilities. Large amounts of data need to be stored and accessed as quickly as possible in today's world. Static random access memory (SRAM) is a type of memory that is frequently utilised in consumer devices. The necessary circuits for designing the read operation for the 88 SRAM array are the 3 to 8 Decoder, Precharge circuit, Write Driver, and Sense amplifier. commence the application of low power approaches to the SRAM cell after that. Here, the SRAM Cell is designed using two low power methods.

High-Performance QC-LDPC Code Co-Processing Approach and VLSI Architecture for Wi-Fi 6

The QC-LDPC code, with its excellent error correction performance and hardware friendliness, has been identified as one of the channel encoding schemes by Wi-Fi 6. Shorting, puncturing, or repeating operations are needed to ensure that user data can be sent with integer symbols and complete rate matching. Due to the uncertainty of the user data size, the modulation’s selectivity, and the difference in the number of spatial streams, the receiver must deal with more than 106 situations. At the same time, other computationally intensive tasks occupy the time slot budget of the receiver. Typical are demodulation and decoding. Hence, the receiver needs to quickly reverse the demodulated data process. This paper first proposes a co-processing method and VLSI architecture compatible with all code lengths, code rates, and processing parameters. The co-processor separates field and block splicing, simplifying the control logic. There is no throughput rate bottleneck, and the maximum delay is less than 1 us.

An area-delay efficient single-precision floating-point multiplier for VLSI systems

The floating-point multiplier (FPM) is the most commonly used component in various image and signal processing applications. An area-delay efficient FPM design could be helpful for the development of high-performance VLSI computing systems. Therefore, this paper presents the analysis of single-precision FPM to find the possibilities for the reduction in delay and area. From the analysis, it is found that the delay of FPM depends on the delay of mantissa multiplication and exponent normalization units. Based on the above observations, in this paper, the delay and area efficient mantissa multiplication and exponent addition-cum-normalization units are proposed. Further, using these components, the single-precision FPM structure is proposed. Synthesis results show that the proposed FPM design offers a saving of 15.3% in delay and 10.8% in area compared to the best available existing FPM design. Besides, the proposed FPM consumes 13.0% less power-delay-product and involves 24.4% less area-delay-product in comparison to the best available existing design. Finally, effectiveness of the proposed single precision floating-point multiplier is presented in Gaussian smoothing filter of the image processing application.

Efficient Approaches to Design Full Adder Using Domino Logic Technique

Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.

Design of a Single-Ended-Write Schmitt-Trigger Based 10T SRAM Cell

Technology scaling is done in order to accommodate more and more transistors in today’s high performance VLSI circuits. These high-performance digital circuits demand large capacity of memory to accomplish faithful operations. However, at scaled technology, SRAM-cell stability is a major issue of concern. Also, increased integration density of these VLSI circuits causes increased power consumption. Leakage power in today’s VLSI circuits has become comparable to dynamic power consumption which also needs to be addressed. In this work, a Schmitt-trigger (ST) based 10T SRAM cell with single-ended-writing and differentially-read feature is proposed. The proposed cell offers enhanced stability and dissipates lower leakage power. Due to separate ports for writing and reading in the proposed cell, the conflict design requirement (which is a condition in conventional 6T cell) is eliminated. Schmitt-trigger based inverters in the proposed cell causes increased threshold voltage of the inverters resulting in enhanced cell stability during read operation. Simulation is carried out on TSPICE using a 65nm Predictive Technology Model (PTM). Results show that the proposed 10T cell provides a 1.7x larger Read static noise margin (RSNM) than the conventional 6T cell. Proposed 10T cell provides Write static noise margin (WSNM) of 155mV during write ‘0’ while 150mV during write ‘1’ operation, respectively, at 0.4V. At a supply voltage of 0.4V, the proposed 10T cell consumes 0.71x lesser static power as compared to that of a conventional 6T cell. However, proposed cell uses more transistors (10 transistors) as compared to that of the conventional 6T cell, therefore, our cell occupies large chip-area as compared to the conventional 6T cell.

Радиационно-стойкие СБИС СнК и ОЗУ — особенности проектирования по КМОП технологиям объемного кремния

The effect of various types of radiation and heavy nuclear particles on VLSI fabricated using CMOS technologies for bulk silicon at a level of 250–90 nm is analyzed. Developed and certified on test crystals (TC) are constructive-topological and circuit solutions for elements of digital libraries, complex-functional RAM blocks and peripheral mixed-signal blocks for designing radiation-hardened VLSI of the “system-on-chip” (SoC) type and RAM of category RT (products with an increased level of radiation resistance). The methodology of radiation-hardened by design (RHBD) has been further developed. For CAD tools, a design environment for VLSI of the RT category was created for manufacturing at Russian factories using available CMOS bulk technologies. Based on this design environment, competitive radiation-hardened high-performance processor CMOS VLSI SoC and VLSI RAM were created. Basic technical solutions are protected by RF patents.

High-Performance VLSI Architecture of DLMS Adaptive Filter for Fast-Convergence and Low-MSE

This brief presents a high-performance VLSI architecture of delayed least mean square (DLMS) adaptive filter for fast-convergence and low-mean square error (MSE) using distributed arithmetic (DA). The proposed design estimates response against the adaptation delays using a parallel predictive adder tree followed by a shift accumulate (SA) unit. An efficient quantization scheme with two bits of scaled error signal is also suggested. Single SA unit for multiple DA bases is used to reduce the number of adders and registers. Simulation and synthesis results show that the proposed design for 32 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order provides 19.72% lesser area, 25.51% lesser power, lesser 28.89% MSE and 59.91% lesser MSE/area over the best existing design.

High performance VLSI architecture for advanced QPSK modems

The article is devoted to the topical issue of creating a high-performance VLSI architecture for advanced QPSK modems. The QPSK modulation scheme is used in VLSI architecture for many high-speed applications such as satellite communications. VLSI is a technology by which 10,000-1 million transistors can be manufactured on a single chip. Since there was a need for additional functions of electronic devices, the development of NVIS technology improved. The proposed architecture is modeled in XILINX software. This software product is specialized tools for programming programmable logic devices in hardware description languages. The main goal of the research is to create a high-performance QPSK module, thanks to which it supports satellite communication with high bandwidth and energy efficiency. A QPSK modulator is a binary (base 2) signal that produces four different sets of input combinations: 00, 01, 10, and 11. Therefore, with QPSK, binary input combinations are combined from two bits. In the proposed project, 8-PSK and 16-PSK modulation with the basics of QPSK modulation and demodulation system were analyzed and modeled to obtain the required output. VERILOG coding was used for program simulation. Verilog is a hardware description language (HDL) used to model electronic systems. Verilog can run on both Windows 7, 8 and Windows 10 operating systems. Errors are coded and checked using XILINX software. This project is implemented to create high performance in NVIS using QPSK, 8-PSK, 16-PSK systems used for satellite communication. Implementing this process in any other module is easy, but in NVIS it is a big challenge.

Switched pseudo-current mirror inverter for low-power, thermally stable and robust ring oscillator

This paper proposes a low-power inverter in 65 nm CMOS technology, which utilizes a switched pseudo-current mirror to control the pull-up network and to reduce the short-circuit current during the transition. This inverter saves 75% power per cycle, while its power-delay product is almost half of the CMOS inverter. The proposed inverter constructs a low-power ring oscillator with improved thermal stability and aging robustness. The proposed structure of a 1.2GHz ring oscillator consumes 0.66mW, while its CMOS counterpart dissipates 4.46mW. The immunity against supply voltage fluctuations is also improved. On the other side, the proposed inverter consumes twice the silicon area and doubles the propagation delay, limiting its usage in high-performance and high-density VLSI applications. These results indicate that the proposed inverter is a viable candidate for special applications, such as ring oscillators used in physically unclonable functions and true random number generators.

A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting

The reconfiguration algorithms have been extensively investigated to ensure the reliability and stability for the processor arrays with faults. It is important to reduce the power consumption, capacitance and communication costs in the processors by reducing the interconnection length of the VLSI array. This paper discusses the reconfiguration problem of the high-performance VLSI processor array under the row and column rerouting constraints. A novel method, making use the idea of network flow, is proposed in this paper. Firstly, a network flow model of the VLSI processor array is constructed, such that the high-performance VLSI target array can be obtained by utilizing the minimal cost flow algorithm. Secondly, we propose a new strategy for bottleneck row selection in the logical array using the minimum cut technique, which can find a more suitable bottleneck row. Finally, we conducted reliable experiments to clearly reveal the efficiency of the new rerouting scheme and algorithm in reducing the number of long interconnects. The experimental results show that, for a host array with size of 256×256, the number of long interconnects in the subarray can be reduced by up to 79.22% and 55.88% without performance penalty for random faults with density of 1% and 25% respectively, when compared with state-of-the-art. In addition, the proposed scheme improves existing algorithm in terms of subarray size. On a 256×256 host array with 25% faulty density, the average improvement in subarray size is up to 3.77% compared with state-of-the-art.

Design of High-Speed Quaternary D Flip-Flop Based on Multiple-valued Current-mode

A new type of quaternary D flip-flop based on multiple-valued current-mode is presented for high-speed sequential circuit in VLSI systems. It employs master-slave mode and dynamic multiple-valued source-coupled logic. A distinguishable multiple-valued interval, fast switch speed and compact structure are obtained by combining source-coupled logic with differential-pair circuit. The performance evaluation is carried out with HSPICE using 0.18μm CMOS process. A performance comparison with those issued in some references is conducted. The delay in our design is about 74% reduced by comparison with the corresponding binary implementation. The circuitry proposed is simplicity, regularity, and modularity, so well suited for VLSI implementation. Quaternary logic seems to be a potential and feasible method of high-performance VLSI systems.

Special issue on SoC and AI processors

Special issue on SoC and AI processors

An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray

Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage of the previous network model and the low-performing of standard network flow algorithms for reconfiguration, the efficiency of these algorithms is poor for constructing the high performance VLSI subarray. In this paper, we present an efficient multiple shortest augmenting paths algorithm for rapidly constructing high performance VLSI array. Firstly, we proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm. Secondly, a multiple shortest augmenting path algorithm based on the new data structure is proposed, which can significant reduce the running time. Finally, we conduct solid experiments to highlight the efficiency of the proposed method in terms of the running time compared to the standard network flow algorithms. The experimental results show that on a 64 × 64 host array with 0.1% faults, the size of the network model can be reduced by about 50% and the average improvements in running time is up to 85.10% compared with four standard network flow algorithms.

A High-Performance VLSI Architecture for a Self-Feedback Convolutional Neural Network

This brief studies the problem of developing an area-time efficient VLSI architecture for a novel self-feedback Convolutional Neural Network (CNN). Self-feedback CNNs offer the promise of high-precision object detection amidst occlusions. However, the size of a typical network required for practical applications presents a challenge for embedded system development. We first present the structure of the self-feedback CNN. We then present an efficient systolic array architecture for the self-feedback CNN with low on-chip memory requirement. The self-feedback CNN has been tested on the KITTI benchmark dataset and it achieves high accuracy for detecting occluded cyclists and pedestrians. FPGA implementation of the proposed architecture on Xilinx Virtex7 XC7VX485T achieves roughly 1.14 Tera Operations per second (TOP/s) at 386 MHz with 9× reduction in on-chip memory requirement compared to recent CNN architectures.

Approximate Adder: Lower-Part or Adder

High-performance VLSI systems are essential in real-time applications, in order to increase the performance of the VLSI systems, an approximate computing technique is followed where the performance of the circuit is enhanced by trading off it with a slight loss in the accuracy. These approximate circuits are used in error-tolerant applications, where output need not be accurate. This paper concentrates mainly on approximate adders, as they are major building blocks of DSP systems. The analysis of the Lower-part OR Adder for 4-bit addition and comparison of it with the precise adder i.e., Ripple Carry Adder using the mentor graphics tool in 90 nm CMOS technology are presented in this paper. Our experimental results show that there is 17%-70% savings in power dissipation, 4%-32% saving in the area, and 19%-84% savings in time due to approximate adder. As the LOA-2 and LOA-3 are performing optimally these two adders can be used for error-tolerant applications and based on the requirement LOA-2 or LOA-3 can be selected.

A High-Performance VLSI Architecture for the PRESENT Lightweight Cryptography

A High-Performance VLSI Architecture for the PRESENT Lightweight Cryptography

ML-Assisted DVFS-Aware HEVC Motion Estimation Design Scheme for Mobile APSoC

High-efficiency video coding (HEVC) is the latest video standard, and a variety of HEVC chips are being incorporated into the application processor system-on-a-chip (APSoC) within mobile devices. However, the coding bandwidth accessed for the motion estimation (ME) operation within HEVC has changed over time because of the adoption of the intelligent power management mechanism within the APSoC. To achieve a low-power high-performance HEVC design, the on-demand coding bandwidth must be considered in the design. In this paper, we develop an intelligent dynamic voltage-frequency-scaling-aware (DVFS-aware) coding-bandwidth-efficient HEVC ME controller algorithm model. We also develop a low-power high-performance VLSI hardware architecture by joining a machine learning (ML) scheme and a convex optimization (CO) method that is adaptive to the time-altering coding bandwidth. The proposed HEVC ME controller design can be integrated into ME to realize a coding bandwidth, coding bit rate, and coding-quality-optimized HEVC ME design for mobile APSoC, therein utilizing an intelligent power management mechanism. The experimental results show the effectiveness of the power and performance of the proposed design.

Design and performance analysis of 6T SRAM cell on different CMOS technologies with stability characterization

With the advent of portable devices, the demand for static random-access memory (SRAM) is increasing with large use of SRAM in System on Chip and high-performance VLSI circuits. SRAM optimization has become a focal point for research work, as 60% to 70% area of the chip is consumed by the memories. The performance parameters optimization can lead to the overall optimization of the performance of the chip. In this paper design and analysis of the 6T SRAM cell at different technologies using PTM (Predictive Technology Model) model has done with the aim of reducing power dissipation while maintaining stability. Then the performance of SRAM cell is compared on the basis of power dissipation i.e. dynamic power dissipation and static power dissipation, delay, Power Delay Product (PDP) and Static Noise Margin (SNM).SRAM cell read stability and write-stability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and Vdd scaling. Cell stability is also examined by the calculation of SNM with the help of the butterfly curve method at different CMOS technologies. Effect of variation of channel length on static power consumption, dynamic power consumption, delay, PDP and SNM is also measured. SNM variation is also observed with the variation of the supply voltage.