High-performance Thin-film Transistors Research Articles

High-performance tin perovskite transistors through formate pseudohalide engineering

The lack of high-performance p-type semiconducting materials hinders the integration of complementary metal-oxide semiconductors with well-established n-type metal-oxide counterparts. Although tin halide perovskites are promising p-type material candidates, their practical implementation is hindered by excessive hole concentrations and difficulties in precisely controlling crystallization, which leads to poor device performance and yield. In this paper, we propose a formate pseudohalide engineering method to overcome these issues and demonstrate high-performance tin perovskite thin-film transistors (TFTs). The incorporation of formate anion greatly suppresses the vacancy defects at the surfaces of the perovskite films with an increase in crystallinity and grain size. This reduces the hole concentration and eliminates the dependence on the addition of excessive tin fluoride for hole suppression. Hence, high-performance TFTs with a high average field-effect hole mobility of 57.34 cm2 V−1 s−1 and on/off current ratios surpassing 108 can be achieved, approaching p-channel low-temperature polysilicon devices.

Role of ultrathin Ti3C2Tx MXene layer for developing solution-processed high-performance low voltage metal oxide transistors

Metal oxide transistors have garnered substantial attention for their potential in low-power electronics, yet challenges remain in achieving both high performance and low operating voltages through solution-based fabrication methods. Optimizing interfacial engineering at the dielectric/semiconductor interface is of utmost importance in the fabrication of high-performance thin film transistors (TFTs). In the present article, a bilayer Ti3C2Tx-MXene/SnO2–semiconductor (Tx stands for surface termination) configuration is used to fabricate a high-performance n-type thin film transistor by using an ion-conducting Li-Al2O3 gate dielectric on a p+-Si substrate, where electrical charges are formed and modulated at the Li-Al2O3/SnO2 interface, and Ti3C2Tx-MXene nanosheets serve as the primary electrical charge channel due to their long lateral size and high mobility. A comparative characterization of two distinct TFTs is conducted, one featuring Ti3C2Tx MXene and SnO2 semiconductor layer and the other with SnO2 only. Notably, the TFT with the Ti3C2Tx MXene layer has shown a significant boost in the carrier mobility (10.6 cm2/V s), leading to remarkable improvements in the on/off ratio (1.3 × 105) and subthreshold swing (194 mV/decade), whereas the SnO2 TFT without the Ti3C2Tx MXene layer shows a mobility of 1.17 cm2/V s with 8.1 × 102 on/off ratio and 387 mV/decade subthreshold swing. This investigation provides a possible way toward the development of high-performance, low-voltage TFT fabrication with the MXene/semiconductor combination.

Non-Volatile Memory Based on ZnO Thin-Film Transistor with Self-Assembled Au Nanocrystals.

Non-volatile memory based on thin-film transistor is crucial for system-on-panel and flexible electronic systems. Achieving high-performance and reliable thin-film transistor (TFT) memory still remains challenging. Here, for the first time, we present a ZnO TFT memory utilizing self-assembled Au nanocrystals with a low thermal budget, exhibiting excellent memory performance, including a program/erase window of 9.8 V, 29% charge loss extrapolated to 10 years, and remarkable endurance characteristics. Moreover, the memory exhibits favorable on-state characteristics with mobility, subthreshold swing, and current on-off ratio of 17.6 cm2V-1s-1, 0.71 V/dec, and 107, respectively. Our study shows that the fabricated TFT memory has great potential for practical applications.

A high-performance organic thin-film transistor with Parylene/PMMA bilayer insulation based on P3HT

This work introduces a pioneering approach in the development of organic thin-film transistors (OTFTs),featuring a double-layer dielectric structure that combines poly(para-xylylene)s (Parylene) and poly(methyl methacrylate) (PMMA) to leverage the high insulation properties and high surface polarity of Parylene with the low insulation properties and low surface polarity of PMMA. This combination results in devices that showcase significantly enhanced electrical performance, including superior charge carrier mobility, increased current on/off ratios, and greater transconductance. Utilizing poly(3-hexylthiophene) (P3HT) for the active layer, the study demonstrates the advantage of the dual dielectric layers in minimizing hysteresis in the transfer curve, thereby facilitating the systematic growth of the organic active layer and enhancing electrical conductivity over single-layer alternatives. The superior performance of the Parylene/PMMA double-layer insulating structure opens new avenues for the advancement of organic electronics, presenting methodologies for performance optimization and expanding the application spectrum of OTFTs.

High-performance ultrathin solution-processed SnO2 top-gate thin-film transistors by constructing high-quality dielectric/channel interface

In this work, we developed a low-thermal-budget approach to realize high-performance solution-processed oxide thin-film transistors (TFTs). To construct high-quality dielectric/channel interface, the corrosion-resistant SnO2 channel and further O2 plasma pre-treatment were adopted to minimize the problematic interface defects. With this strategy, the afforded solution-processed SnO2 TFTs exhibited improved electrical performance and stability, including a descent field-effect mobility (μFE) of 21.4 cm2/V·s, high on/off ratio (Ion/Ioff) of 109, positive threshold voltage (Vth) of 0.39 V, steep SS of 94.7 mV/dec, and small ΔVth of 0.08 and −0.03 V under PBS and NBS, respectively. This work demonstrates a promising fabrication approach for solution-processed oxide TFTs towards advanced applications.

Selenium-alloyed tellurium oxide for amorphous p-channel transistors.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. 1), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm2 V-1 s-1 and on/off current ratios of 106-107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

High-performance nano-scale InSnO transistors

Nanoscale short-channel oxide thin film transistors (TFTs) have attracted widespread research interest due to their potential applications in advanced display and memory devices. In this work, we fabricate 10 μm channel length indium-tin-oxide (ITO) TFTs and analyze the uniformity and repeatability of ITO TFTs at the long channel range. Then we fabricate ITO TFTs with a series of channel lengths ranging from 10 μm to 150 nm and through an optimized process we finally fabricate 130 nm channel length high-performance ITO TFTs with an on-state current of 93 (μA/μm), a subthreshold swing of 102 (mV decade–1), and on/off ratio over 107 at a drain voltage of 3 V.

All-Solution-Processed High-Performance MoS2 Thin-Film Transistors with a Quasi-2D Perovskite Oxide Dielectric.

Assembling solution-processed van der Waals (vdW) materials into thin films holds great promise for constructing large-scale, high-performance thin-film electronics, especially at low temperatures. While transition metal dichalcogenide thin films assembled in solution have shown potential as channel materials, fully solution-processed vdW electronics have not been achieved due to the absence of suitable dielectric materials and high-temperature processing. In this work, we report on all-solution-processedvdW thin-film transistors (TFTs) comprising molybdenum disulfides (MoS2) as the channel and Dion-Jacobson-phase perovskite oxides as the high-permittivity dielectric. The constituent layers are prepared as colloidal solutions through electrochemical exfoliation of bulk crystals, followed by sequential assembly into a semiconductor/dielectric heterostructure for TFT construction. Notably, all fabrication processes are carried out at temperatures below 250 °C. The fabricated MoS2 TFTs exhibit excellent device characteristics, including high mobility (>10 cm2 V-1 s-1) and an on/off ratio exceeding 106. Additionally, the use of a high-k dielectric allows for operation at low voltage (∼5 V) and leakage current (∼10-11 A), enabling low power consumption. Our demonstration of the low-temperature fabrication of high-performance TFTs presents a cost-effective and scalable approach for heterointegrated thin-film electronics.

Low voltage-driven, high-performance TiO2 thin film transistors with MHz switching speed.

High-speed circuits based on thin film transistors (TFTs) show promising potential applications in biomedical imaging and human-machine interactions. One of the critical requirements for high-speed electronic devices lies in high-frequency switching or amplification at low voltages, typically driven by batteries (∼3.0 V). To date, however, most electrical performances of metal oxide TFTs are measured under direct current (DC) conditions, and their dynamic switching behaviour is scarcely explored and studied systematically. Here in this work, we present low voltage-driven, high-performance TiO2 thin film transistors, which can be operated at a switching speed of MHz. Our proposed TiO2 TFTs demonstrated a high on-off ratio of 107, together with a subthreshold swing (SS) of ∼150 mV Dec-1 averaged over four orders of magnitude, which can be further reduced below 100 mV Dec-1 when the temperature cools to 77 K. Additionally, the TiO2 TFTs exhibit excellent gate-pulse switching at various frequencies ranging from 1.0 Hz to 1.0 MHz. We also explored the potential application of the TiO2 TFTs as logic gates by constructing a resistive-loaded inverter, which shows stable operation at 10 kHz frequency and various temperatures. Thus, our results show the great potential of TiO2 TFTs as a new platform for high-speed electronic applications.

Order of magnitude improvement in the transport performance of carbon nanotube films by completely removing surfactants

Surfactant-based separation techniques have been developed for the high-efficiency production of high-purity semiconducting single-wall carbon nanotubes (s-SWCNTs), which establish an important material foundation for the preparation of high-performance carbon-based electronic devices. However, surfactant molecules wrapping around SWCNTs during structural separation inevitably degrade the resulting device performances due to increasing contact resistance between the SWCNTs and electrodes and between individual SWCNTs. Here, we developed a simple and effective strategy for completely removing the surfactant molecules around separated s-SWCNTs by annealing and rinsing. With this technique, defects were not clearly increased in the crystal structure of SWCNTs, and the transport performances of SWCNT-based thin film transistors (TFTs), including the on-state current and mobility, were improved by approximately an order of magnitude, while the on-off ratio increased by nearly 1.5 orders of magnitude. Upon shortening of the channel lengths of the devices, high-performance TFTs were fabricated based on an increase in the proportion of individualized SWCNTs that directly connected the source and drain electrodes. The present technique provides an important foundation for promoting the development of carbon-based electronic devices.

High-performance thin-film transistors based on aligned carbon nanotubes for mini- and micro-LED displays

Inorganic mini-LEDs (mLEDs) and micro-LEDs (μLEDs) have ultrahigh luminance and long lifetimes, and are challenging liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays for next-generation displays. Backplane thin-film transistors (TFTs) for mLED/μLED displays with high mobility and large driving current are under development as currently widely used backplane active materials such as crystalline silicon (CMOS Si), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and metal oxides are facing difficulties to meet the requirements. Semiconducting carbon nanotubes (s-CNTs) have long been considered as promising materials for TFTs because of their unique electronic properties. However, TFTs based on s-CNT random networks show inadequate performance due to large amounts of inter-tube junctions. Here, we report high performance TFTs based on wafer-scale, high-density aligned s-CNT array (A-CNT) for mLED/μLED driving backplanes. These A-CNT TFTs with micrometer scale channel length were fabricated using standard semiconductor manufacturing process, and exhibited mobility as high as 160 cm2/Vs and driving current as large as 417 μA/μm at operation voltage of ∼3 V, exceeding commercially available TFTs with similar device sizes. In addition, these A-CNT TFTs have demonstrated good driving capability for commercial mLEDs in a one-transistor-one-diode (1T1D) pixel circuit configuration, and been capable of driving commercially available mLED/μLED displays. Moreover, a prototype display with 2 × 2 mLED array have been demonstrated with full control of each pixel, manifesting the great potential for A-CNT TFT technology for backplane of mLED/μLED displays.

Photolithographic Rugged Electrode for High-Density Low-Contact-Resistance Coplanar Organic Transistors.

The realization of high-performance photolithographic coplanar organic thin film transistors (OTFTs) is fundamental to boost cosmicallycommercial applications of organic electronics. However, photolithographic coplanar OTFTs generally suffer from poor charge injection and therefore poor filed-effect performance. Here, a simple and effective strategy is developed to fabricate photolithographic rugged electrodes, and successfully achieve high-density low-contact-resistance photolithographic coplanar OTFTs. Based on this versatile electrode, the wafer-scale photolithographic rugged electrode can be easily achieved, and the device density of the coplanar OTFTs is as high as 28000cm-2 . The device shows excellent electrical properties with mobility up to 2.01cm2 V-1 s-1 and Rc as low as 7.8kΩcm, which is superior to all the reported Ag-electrode coplanar OTFTs. This work shows a reliable strategy to reduce the contact resistance of photolithographic coplanar OTFTs and elucidates the effect of injection resistance (Rinj ) and access resistance (Racc ) on coplanar OTFTs.

Atomically Thin Amorphous Indium-Oxide Semiconductor Film Developed Using a Solution Process for High-Performance Oxide Transistors.

High-performance oxide transistors have recently attracted significant attention for use in various electronic applications, such as displays, sensors, and back-end-of-line transistors. In this study, we demonstrate atomically thin indium-oxide (InOx) semiconductors using a solution process for high-performance thin-film transistors (TFTs). To achieve superior field-effect mobility and switching characteristics in TFTs, the bandgap and thickness of the InOx were tuned by controlling the InOx solution molarity. As a result, a high field-effect mobility and on/off-current ratio of 13.95 cm2 V-1 s-1 and 1.42 × 1010, respectively, were achieved using 3.12-nanometer-thick InOx. Our results showed that the charge transport of optimized InOx with a thickness of 3.12 nm is dominated by percolation conduction due to its low surface roughness and appropriate carrier concentration. Furthermore, the atomically thin InOx TFTs showed superior positive and negative gate bias stress stabilities, which are important in electronic applications. The proposed oxide TFTs could provide an effective means of the fabrication of scalable, high-throughput, and high-performance transistors for next-generation electronic applications.

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

As-Grown Crystalline InGaZnO by Spray Pyrolysis on a Flexible Substrate for a Thin-Film Transistor with Excellent Stability.

The development of low-cost, high-mobility oxide thin-film transistors (TFTs) with excellent stability is of increasing interest. The coplanar oxide TFTs can be used for high-speed, large-area, and high-resolution displays. Here, we report highly oriented, as-grown crystalline InGaZnO (c-IGZO) with very low oxygen vacancy defects using spray pyrolysis at the substrate temperature of 425 °C. The c-IGZO exhibits a highly oriented, c-axis aligned crystal perpendicular to the substrate with a high mass density of 6.73 g cm-3 without any disordered incubation layer. Its resistivity can be decreased to 0.42 mΩ cm by NF3 plasma doping, which is essential to achieving high-performance coplanar TFT. We have demonstrated the application of this material to high-performance flexible TFTs. The self-aligned, coplanar c-IGZO TFTs on the polyimide substrate exhibit an average field-effect mobility of 39.60 cm2 V-1 s-1, threshold voltage of -1.00 V, subthreshold swing of 0.21 V dec-1, and on/off current ratio over 108. The ring oscillator and gate driver made of the c-IGZO TFTs exhibit a propagation delay of 8.77 ns/stage and rising/falling times of 648/564 ns, respectively. Therefore, the as-grown c-IGZO by spray pyrolysis has the potential to be utilized as a new oxide semiconductor for the production of low-cost, flexible TFT electronics.

Utilizing Dip-Coating to Fabricate Gate Dielectric and Semiconductor for Thin-Film Transistors

The potential applications of advanced electronic materials in large-area, printable, and flexible electronics have generated significant interest. However, creating high-performance, low-voltage thin-film transistors (TFTs) for these applications remains difficult due to a lack of advanced gate dielectric and semiconductor materials that meet both ease-of-fabrication requirements and high electrical performance. In this study, we present high-performance gate dielectric thin-films, which were fabricated using a facile solution-based technique, and then employed to realize low operating voltage organic and metal oxide semiconductor-based thin-film transistors. The high-k oxide gate dielectrics were produced via a simple dip-coating method, resulting in the formation of thin-oxide layers. These novel oxide gate dielectrics demonstrated exceptional dielectric properties, with large capacitances (up to 430 nF/ cm2), low-level leakage current densities (< 3 × 10-8A/cm2 at 4 V), featureless morphology (rms roughness < 0.36 nm), and high transparency (> 85%). Consequently, these dip-coated gate dielectrics can be incorporated into thin-film transistors, utilizing pentacene as p-type organic semiconductors. Furthermore, by employing dip-coating, indium oxide and indium-gallium-zinc oxide can be utilized as n-type inorganic semiconductors, allowing for the fabrication of low-voltage operation and high-performance inorganic TFTs. The resulting TFTs functioned at ultralow voltages (< ± 2 V) and achieved high transistor performance (hole mobility: 0.28 cm2V-1·s-1, electron mobility: ~2.0 cm2V-1·s-1 and on/off current ratio >105).

Interfacial molecular screening of polyimide dielectric towards high-performance organic field-effect transistors

The compatibility of the gate dielectrics with semiconductors is vital for constructing efficient conducting channel for high charge transport. However, it is still a highly challenging mission to clearly clarify the relationship between the dielectric layers and the chemical structure of semiconductors, especially vacuum-deposited small molecules. Here, interfacial molecular screening of polyimide (Kapton) dielectric in organic field-effect transistors (OFETs) is comprehensively studied. It is found that the semiconducting small molecules with alkyl side chains prefer to form a high-quality charge transport layer on polyimide (PI) dielectrics compared with the molecules without alkyl side chains. On this basis, the fabricated transistors could reach the mobility of 1.2 cm2 V−1 s−1 the molecule with alkyl side chains on bare PI dielectric. What is more, the compatible semiconductor and dielectric would further produce a low activation energy (EA) of 3.01 meV towards efficient charge transport even at low temperature (e.g., 100 K, 0.9 cm2 V−1 s−1). Our research provides a guiding scheme for the construction of high-performance thin-film field-effect transistors based on PI dielectric layer at room and low temperatures.

All-Solution-Driven Thin-Film Transistor With Low Power Dissipation for Logic Electronics and Neuronal Synapse

For the realization of low-power consumption brain-inspired neuromorphic devices which mimic the biological neuronal information processing methodology, the development of transistors capable of synaptic behaviors and neuronal computation has attracted widespread attention. However, ultrathin, solid-state neuromorphic devices with ultralow energy consumption are still in the exploration stage. Herein, based on an all-solution strategy, oxide-based electrical-double-layer (EDL) thin film transistors (TFTs) have been constructed, demonstrating good operational stability and excellent logic operation functions. Motivated by these excellent characteristics, the TFTs devices triggered by electrical pulses can mimic synaptic behaviors, including excitatory postsynaptic current (EPSC) and paired-pulse facilitation (PPF). In addition, response to electrical stimulus, high-pass filtering characteristics, and short-term memory (STM) and long-term memory (LTM) characteristics have been achieved and investigated. These results reported here have demonstrated that all-solution-driven high-performance oxide-based TFTs enable the achievement of logic electronics with low-power consumption and brain-inspired neuromorphic devices.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

Selectively Nitrogen Doped ALD-IGZO TFTs with Extremely High Mobility and Reliability.

Achieving high mobility and reliability in atomic layer deposition (ALD)-based IGZO thin-film transistors (TFTs) with an amorphous phase is vital for practical applications in relevant fields. Here, we suggest a method to effectively increase stability while maintaining high mobility by employing the selective application of nitrous oxide plasma reactant during plasma-enhanced ALD (PEALD) at 200 °C process temperature. The nitrogen-doping mechanism is highly dependent on the intrinsic carbon impurities or nature of each cation, as demonstrated by a combination of theoretical and experimental research. The Ga2O3 subgap states are especially dependent on plasma reactants. Based on these insights, we can obtain high-performance indium-rich PEALD-IGZO TFTs (threshold voltage: -0.47 V; field-effect mobility: 106.5 cm2/(V s); subthreshold swing: 113.5 mV/decade; hysteresis: 0.05 V). In addition, the device shows minimal threshold voltage shifts of +0.45 and -0.10 V under harsh positive/negative bias temperature stress environments (field stress: ±2 MV/cm; temperature stress: 95 °C) after 10000 s.