High-performance Thin-film Transistors Research Articles

Novel solution-gated transistor sensor-based SnO2 epitaxial thin films grown by pulsed laser deposition for nitrite detection.

A solution-gate controlled thin-film transistor with SnO2 epitaxial thin films (SnO2-SGTFT) is successfully utilized for highly sensitive detection of nitrite. The SnO2 films are deposited as channel materials on a c-plane sapphire (c-Al2O3) substrate through pulsed laser deposition (PLD), with superior crystal quality and out-of-plane atomic ordering. PtAu NPs/rGO nanocomposites are electrodeposited on agold electrode to function as a transistor gate to further enhance the nitrite catalytic performance of thedevice. The change in effective gate voltage due to the electrooxidation of nitrite on the gate electrode is the primary sensing mechanism of the device. Based on the inherent amplification effect of transistors, the superior electrical properties of SnO2, and the high electrocatalytic activity of PtAu NPs/rGO, the SnO2-SGTFT sensor has a low detection limit of 0.1nM and a wide linear detection range of 0.1nM ~ 50mM at VGS = 1.0V. Furthermore, the sensor has excellent characteristics such as rapid response time, selectivity, and stability. The practicability of the device has been confirmed by the quantitative detection of nitrite in natural lake water. SnO2 epitaxial films grown by PLD provide a simple and efficient way to fabricate nitrite SnO2-SGTFT sensors in environmental monitoring and food safety, among others. It also provides a reference for the construction of other high-performance thin-film transistor sensors.

Junctionless Structure Indium-Tin Oxide Thin-Film Transistors Enabling Enhanced Mechanical and Contact Stability.

In recent years, considerable attention has focused on high-performance and flexible crystalline metal oxide thin-film transistors (TFTs). However, achieving both high performance and flexibility in semiconductor devices is challenging due to the inherently conductive and brittle nature of crystalline metal oxide. In this study, we propose a facile way to overcome this limitation by employing a junctionless (JL) TFT structure via oxygen plasma treatment of the crystalline indium-tin oxide (ITO) films. The oxygen plasma treatment significantly reduced oxygen vacancies in the ITO films, contributing to the significant reduction in the carrier concentration from 4.67 × 1020 to 1.39 × 1016. Importantly, this reduction was achieved without inducing any noticeable structural changes in the ITO, enabling the successful realization of ITO JL TFTs with an adjustable threshold voltage. Furthermore, the ITO JL TFTs demonstrate good stability and reliability under various bias stress conditions, aging in the air atmosphere, and high-temperature processes. In addition, the ITO JL TFTs exhibit low light sensitivity due to the wide bandgap of ITO and further suppression of Vo defects, making them suitable for applications requiring stable performance under light exposure. To compare and analyze the flexibility of the JL structure and conventional structure with additional source/drain (S/D) junction in ITO TFTs with nonencapsulation, we utilized mechanical simulations and transmission line method (TLM). By employing the JL structure in ITO TFT through carefully optimized oxygen plasma treatment, we successfully mitigated stress concentration at the S/D-channel interface. This resulted in a JL ITO TFT that exhibited a change in contact resistance of less than 20% even after 20,000 bending cycles. Consequently, a stable and flexible ITO TFT with field-effect mobility (μFE) of 12.74 cm2/(V s) was realized, outperforming conventionally structured ITO TFTs with additional S/D junction, where the contact resistance nearly tripled.

High-Performance Tin Oxide Thin-Film Transistors Realized by Codoping and Their Application in Logic Circuits.

Tin oxide is a promising channel material, offering the advantages of being low-cost and environmentally friendly and having a wide band gap. However, despite the high electron mobility of SnO2 in bulk, the corresponding thin-film transistors (TFTs) generally exhibit moderate performance, hindering their widespread application. Herein, we proposed a codoping strategy to improve both the electrical property and the stability of SnO2 TFTs. A comparative analysis between doped and undoped SnO2 was conducted. It is observed that taking advantage of the difference in ionic radii between two dopants (indium and gallium) and the tin ions in the host lattice can effectively reduce impurity-induced strain. Additionally, we investigated the effect of codoping content on SnO2 TFTs. The optimal codoped SnO2 (TIGO) TFTs demonstrate high performance, featuring a field-effect mobility of 15.9 cm2/V·s, a threshold voltage of 0.2 V, a subthreshold swing of 0.5 V/decade, and an on-to-off current ratio of 2.2 × 107. Furthermore, the devices show high stability under both positive and negative bias stress conditions with a small threshold voltage shift of 1.8 and -1.2 V, respectively. Utilizing the TIGO TFTs, we successfully constructed a resistor-loaded unipolar inverter with a high gain of 10.76. This study highlights the potential of codoped SnO2 TFTs for advanced applications in electronic devices.

One-volt oxide based complementary circuit

In low-power electronics, there is a substantial demand for high-performance p-type oxide thin-film transistors (TFTs) that are capable of efficient operation at low voltages. In this study, we employ anodization to form an aluminum oxide gate dielectric layer, enabling the fabrication of p-type tin oxide (SnO) TFTs that effectively operate at a low voltage of 1 V. Under optimal device fabrication conditions, the SnO TFT demonstrates an on/off current ratio exceeding 103 and a saturation mobility of 1.94 cm2 V−1 s−1 at 1 V operation. The optimal SnO TFT fabrication conditions are subsequently used to fabricate a complementary inverter, comprising a SnO TFT and an n-type indium gallium zinc oxide TFT, achieving a gain of up to 38 at a 1 V supply voltage. Notably, the inverter’s switching point voltage is finely tuned to the ideal value, precisely half of the supply voltage. This oxide-based complementary inverter showcases promising potential in low-power electronics.

Fully atomic layer deposition induced InAlO thin film transistors

The atomic layer deposition (ALD) technique has been extensively utilized for depositing metal oxide (MO) thin films, particularly as gate insulators in thin film transistors (TFTs). However, research on MO semiconductors as channel layer materials in TFTs using ALD is limited, especially for fully ALD-fabricated MO TFTs. In this study, fully ALD-fabricated InAlO TFTs were developed, with optimized aluminum doping content and annealing temperature to enhance the electrical properties and stability. The InAlO TFTs, fabricated with a cycle ratio of 15:1 and annealed at 350 °C, exhibit superior performance, including a field-effect mobility of 7.2 cm2/V·s, a subthreshold swing of 165 mV/decade, and an on/off current ratio of 2.3 × 106, with a threshold voltage of only 0.1 V. Additionally, they demonstrated good stability, with a threshold voltage shift of 0.11 V under positive bias stress. The improved electrical properties and stability are attributed to reduced carrier concentration and the inhibition of oxygen defect generation, achieved through appropriate annealing temperatures and aluminum doping. Thus, the development of fully ALD-fabricated high-performance TFTs holds promise for next-generation display technologies as pixel-driving circuits.

High-performance tin perovskite transistors through formate pseudohalide engineering

The lack of high-performance p-type semiconducting materials hinders the integration of complementary metal-oxide semiconductors with well-established n-type metal-oxide counterparts. Although tin halide perovskites are promising p-type material candidates, their practical implementation is hindered by excessive hole concentrations and difficulties in precisely controlling crystallization, which leads to poor device performance and yield. In this paper, we propose a formate pseudohalide engineering method to overcome these issues and demonstrate high-performance tin perovskite thin-film transistors (TFTs). The incorporation of formate anion greatly suppresses the vacancy defects at the surfaces of the perovskite films with an increase in crystallinity and grain size. This reduces the hole concentration and eliminates the dependence on the addition of excessive tin fluoride for hole suppression. Hence, high-performance TFTs with a high average field-effect hole mobility of 57.34 cm2 V−1 s−1 and on/off current ratios surpassing 108 can be achieved, approaching p-channel low-temperature polysilicon devices.

Role of ultrathin Ti3C2Tx MXene layer for developing solution-processed high-performance low voltage metal oxide transistors

Metal oxide transistors have garnered substantial attention for their potential in low-power electronics, yet challenges remain in achieving both high performance and low operating voltages through solution-based fabrication methods. Optimizing interfacial engineering at the dielectric/semiconductor interface is of utmost importance in the fabrication of high-performance thin film transistors (TFTs). In the present article, a bilayer Ti3C2Tx-MXene/SnO2–semiconductor (Tx stands for surface termination) configuration is used to fabricate a high-performance n-type thin film transistor by using an ion-conducting Li-Al2O3 gate dielectric on a p+-Si substrate, where electrical charges are formed and modulated at the Li-Al2O3/SnO2 interface, and Ti3C2Tx-MXene nanosheets serve as the primary electrical charge channel due to their long lateral size and high mobility. A comparative characterization of two distinct TFTs is conducted, one featuring Ti3C2Tx MXene and SnO2 semiconductor layer and the other with SnO2 only. Notably, the TFT with the Ti3C2Tx MXene layer has shown a significant boost in the carrier mobility (10.6 cm2/V s), leading to remarkable improvements in the on/off ratio (1.3 × 105) and subthreshold swing (194 mV/decade), whereas the SnO2 TFT without the Ti3C2Tx MXene layer shows a mobility of 1.17 cm2/V s with 8.1 × 102 on/off ratio and 387 mV/decade subthreshold swing. This investigation provides a possible way toward the development of high-performance, low-voltage TFT fabrication with the MXene/semiconductor combination.

Non-Volatile Memory Based on ZnO Thin-Film Transistor with Self-Assembled Au Nanocrystals.

Non-volatile memory based on thin-film transistor is crucial for system-on-panel and flexible electronic systems. Achieving high-performance and reliable thin-film transistor (TFT) memory still remains challenging. Here, for the first time, we present a ZnO TFT memory utilizing self-assembled Au nanocrystals with a low thermal budget, exhibiting excellent memory performance, including a program/erase window of 9.8 V, 29% charge loss extrapolated to 10 years, and remarkable endurance characteristics. Moreover, the memory exhibits favorable on-state characteristics with mobility, subthreshold swing, and current on-off ratio of 17.6 cm2V-1s-1, 0.71 V/dec, and 107, respectively. Our study shows that the fabricated TFT memory has great potential for practical applications.

A high-performance organic thin-film transistor with Parylene/PMMA bilayer insulation based on P3HT

This work introduces a pioneering approach in the development of organic thin-film transistors (OTFTs),featuring a double-layer dielectric structure that combines poly(para-xylylene)s (Parylene) and poly(methyl methacrylate) (PMMA) to leverage the high insulation properties and high surface polarity of Parylene with the low insulation properties and low surface polarity of PMMA. This combination results in devices that showcase significantly enhanced electrical performance, including superior charge carrier mobility, increased current on/off ratios, and greater transconductance. Utilizing poly(3-hexylthiophene) (P3HT) for the active layer, the study demonstrates the advantage of the dual dielectric layers in minimizing hysteresis in the transfer curve, thereby facilitating the systematic growth of the organic active layer and enhancing electrical conductivity over single-layer alternatives. The superior performance of the Parylene/PMMA double-layer insulating structure opens new avenues for the advancement of organic electronics, presenting methodologies for performance optimization and expanding the application spectrum of OTFTs.

High-performance ultrathin solution-processed SnO2 top-gate thin-film transistors by constructing high-quality dielectric/channel interface

In this work, we developed a low-thermal-budget approach to realize high-performance solution-processed oxide thin-film transistors (TFTs). To construct high-quality dielectric/channel interface, the corrosion-resistant SnO2 channel and further O2 plasma pre-treatment were adopted to minimize the problematic interface defects. With this strategy, the afforded solution-processed SnO2 TFTs exhibited improved electrical performance and stability, including a descent field-effect mobility (μFE) of 21.4 cm2/V·s, high on/off ratio (Ion/Ioff) of 109, positive threshold voltage (Vth) of 0.39 V, steep SS of 94.7 mV/dec, and small ΔVth of 0.08 and −0.03 V under PBS and NBS, respectively. This work demonstrates a promising fabrication approach for solution-processed oxide TFTs towards advanced applications.

Selenium-alloyed tellurium oxide for amorphous p-channel transistors.

Compared to polycrystalline semiconductors, amorphous semiconductors offer inherent cost-effective, simple and uniform manufacturing. Traditional amorphous hydrogenated Si falls short in electrical properties, necessitating the exploration of new materials. The creation of high-mobility amorphous n-type metal oxides, such as a-InGaZnO (ref. 1), and their integration into thin-film transistors (TFTs) have propelled advancements in modern large-area electronics and new-generation displays2-8. However, finding comparable p-type counterparts poses notable challenges, impeding the progress of complementary metal-oxide-semiconductor technology and integrated circuits9-11. Here we introduce a pioneering design strategy for amorphous p-type semiconductors, incorporating high-mobility tellurium within an amorphous tellurium suboxide matrix, and demonstrate its use in high-performance, stable p-channel TFTs and complementary circuits. Theoretical analysis unveils a delocalized valence band from tellurium 5p bands with shallow acceptor states, enabling excess hole doping and transport. Selenium alloying suppresses hole concentrations and facilitates the p-orbital connectivity, realizing high-performance p-channel TFTs with an average field-effect hole mobility of around 15 cm2 V-1 s-1 and on/off current ratios of 106-107, along with wafer-scale uniformity and long-term stabilities under bias stress and ambient ageing. This study represents a crucial stride towards establishing commercially viable amorphous p-channel TFT technology and complementary electronics in a low-cost and industry-compatible manner.

High-performance nano-scale InSnO transistors

Nanoscale short-channel oxide thin film transistors (TFTs) have attracted widespread research interest due to their potential applications in advanced display and memory devices. In this work, we fabricate 10 μm channel length indium-tin-oxide (ITO) TFTs and analyze the uniformity and repeatability of ITO TFTs at the long channel range. Then we fabricate ITO TFTs with a series of channel lengths ranging from 10 μm to 150 nm and through an optimized process we finally fabricate 130 nm channel length high-performance ITO TFTs with an on-state current of 93 (μA/μm), a subthreshold swing of 102 (mV decade–1), and on/off ratio over 107 at a drain voltage of 3 V.

All-Solution-Processed High-Performance MoS2 Thin-Film Transistors with a Quasi-2D Perovskite Oxide Dielectric.

Assembling solution-processed van der Waals (vdW) materials into thin films holds great promise for constructing large-scale, high-performance thin-film electronics, especially at low temperatures. While transition metal dichalcogenide thin films assembled in solution have shown potential as channel materials, fully solution-processed vdW electronics have not been achieved due to the absence of suitable dielectric materials and high-temperature processing. In this work, we report on all-solution-processedvdW thin-film transistors (TFTs) comprising molybdenum disulfides (MoS2) as the channel and Dion-Jacobson-phase perovskite oxides as the high-permittivity dielectric. The constituent layers are prepared as colloidal solutions through electrochemical exfoliation of bulk crystals, followed by sequential assembly into a semiconductor/dielectric heterostructure for TFT construction. Notably, all fabrication processes are carried out at temperatures below 250 °C. The fabricated MoS2 TFTs exhibit excellent device characteristics, including high mobility (>10 cm2 V-1 s-1) and an on/off ratio exceeding 106. Additionally, the use of a high-k dielectric allows for operation at low voltage (∼5 V) and leakage current (∼10-11 A), enabling low power consumption. Our demonstration of the low-temperature fabrication of high-performance TFTs presents a cost-effective and scalable approach for heterointegrated thin-film electronics.

Low voltage-driven, high-performance TiO2 thin film transistors with MHz switching speed.

High-speed circuits based on thin film transistors (TFTs) show promising potential applications in biomedical imaging and human-machine interactions. One of the critical requirements for high-speed electronic devices lies in high-frequency switching or amplification at low voltages, typically driven by batteries (∼3.0 V). To date, however, most electrical performances of metal oxide TFTs are measured under direct current (DC) conditions, and their dynamic switching behaviour is scarcely explored and studied systematically. Here in this work, we present low voltage-driven, high-performance TiO2 thin film transistors, which can be operated at a switching speed of MHz. Our proposed TiO2 TFTs demonstrated a high on-off ratio of 107, together with a subthreshold swing (SS) of ∼150 mV Dec-1 averaged over four orders of magnitude, which can be further reduced below 100 mV Dec-1 when the temperature cools to 77 K. Additionally, the TiO2 TFTs exhibit excellent gate-pulse switching at various frequencies ranging from 1.0 Hz to 1.0 MHz. We also explored the potential application of the TiO2 TFTs as logic gates by constructing a resistive-loaded inverter, which shows stable operation at 10 kHz frequency and various temperatures. Thus, our results show the great potential of TiO2 TFTs as a new platform for high-speed electronic applications.

Flexible Metal Oxide Thin-Film Transistors Produced by Nanofiber-to-Film Process

With the rapid technology development of the thin-film transistors (TFTs), the TFTs based on silicon are facing inherent limitations. Finding suitable materials and developing new techniques for fabricating high-performance TFTs...

Order of magnitude improvement in the transport performance of carbon nanotube films by completely removing surfactants

Surfactant-based separation techniques have been developed for the high-efficiency production of high-purity semiconducting single-wall carbon nanotubes (s-SWCNTs), which establish an important material foundation for the preparation of high-performance carbon-based electronic devices. However, surfactant molecules wrapping around SWCNTs during structural separation inevitably degrade the resulting device performances due to increasing contact resistance between the SWCNTs and electrodes and between individual SWCNTs. Here, we developed a simple and effective strategy for completely removing the surfactant molecules around separated s-SWCNTs by annealing and rinsing. With this technique, defects were not clearly increased in the crystal structure of SWCNTs, and the transport performances of SWCNT-based thin film transistors (TFTs), including the on-state current and mobility, were improved by approximately an order of magnitude, while the on-off ratio increased by nearly 1.5 orders of magnitude. Upon shortening of the channel lengths of the devices, high-performance TFTs were fabricated based on an increase in the proportion of individualized SWCNTs that directly connected the source and drain electrodes. The present technique provides an important foundation for promoting the development of carbon-based electronic devices.

High-performance thin-film transistors based on aligned carbon nanotubes for mini- and micro-LED displays

Inorganic mini-LEDs (mLEDs) and micro-LEDs (μLEDs) have ultrahigh luminance and long lifetimes, and are challenging liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays for next-generation displays. Backplane thin-film transistors (TFTs) for mLED/μLED displays with high mobility and large driving current are under development as currently widely used backplane active materials such as crystalline silicon (CMOS Si), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and metal oxides are facing difficulties to meet the requirements. Semiconducting carbon nanotubes (s-CNTs) have long been considered as promising materials for TFTs because of their unique electronic properties. However, TFTs based on s-CNT random networks show inadequate performance due to large amounts of inter-tube junctions. Here, we report high performance TFTs based on wafer-scale, high-density aligned s-CNT array (A-CNT) for mLED/μLED driving backplanes. These A-CNT TFTs with micrometer scale channel length were fabricated using standard semiconductor manufacturing process, and exhibited mobility as high as 160 cm2/Vs and driving current as large as 417 μA/μm at operation voltage of ∼3 V, exceeding commercially available TFTs with similar device sizes. In addition, these A-CNT TFTs have demonstrated good driving capability for commercial mLEDs in a one-transistor-one-diode (1T1D) pixel circuit configuration, and been capable of driving commercially available mLED/μLED displays. Moreover, a prototype display with 2 × 2 mLED array have been demonstrated with full control of each pixel, manifesting the great potential for A-CNT TFT technology for backplane of mLED/μLED displays.

Photolithographic Rugged Electrode for High-Density Low-Contact-Resistance Coplanar Organic Transistors.

The realization of high-performance photolithographic coplanar organic thin film transistors (OTFTs) is fundamental to boost cosmicallycommercial applications of organic electronics. However, photolithographic coplanar OTFTs generally suffer from poor charge injection and therefore poor filed-effect performance. Here, a simple and effective strategy is developed to fabricate photolithographic rugged electrodes, and successfully achieve high-density low-contact-resistance photolithographic coplanar OTFTs. Based on this versatile electrode, the wafer-scale photolithographic rugged electrode can be easily achieved, and the device density of the coplanar OTFTs is as high as 28000cm-2 . The device shows excellent electrical properties with mobility up to 2.01cm2 V-1 s-1 and Rc as low as 7.8kΩcm, which is superior to all the reported Ag-electrode coplanar OTFTs. This work shows a reliable strategy to reduce the contact resistance of photolithographic coplanar OTFTs and elucidates the effect of injection resistance (Rinj ) and access resistance (Racc ) on coplanar OTFTs.

Atomically Thin Amorphous Indium-Oxide Semiconductor Film Developed Using a Solution Process for High-Performance Oxide Transistors.

High-performance oxide transistors have recently attracted significant attention for use in various electronic applications, such as displays, sensors, and back-end-of-line transistors. In this study, we demonstrate atomically thin indium-oxide (InOx) semiconductors using a solution process for high-performance thin-film transistors (TFTs). To achieve superior field-effect mobility and switching characteristics in TFTs, the bandgap and thickness of the InOx were tuned by controlling the InOx solution molarity. As a result, a high field-effect mobility and on/off-current ratio of 13.95 cm2 V-1 s-1 and 1.42 × 1010, respectively, were achieved using 3.12-nanometer-thick InOx. Our results showed that the charge transport of optimized InOx with a thickness of 3.12 nm is dominated by percolation conduction due to its low surface roughness and appropriate carrier concentration. Furthermore, the atomically thin InOx TFTs showed superior positive and negative gate bias stress stabilities, which are important in electronic applications. The proposed oxide TFTs could provide an effective means of the fabrication of scalable, high-throughput, and high-performance transistors for next-generation electronic applications.

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors

Synthesis of a Tellurium Semiconductor with an Organic–Inorganic Hybrid Passivation Layer for High-Performance p-Type Thin Film Transistors